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文件名称:project_fir_test

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Linux] [SHELL] [源码]
  • 上传时间：
    2017-04-17
  • 文件大小：
    37.35mb
  • 已下载：
    0次
  • 提 供 者：
    k****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
(系统自动生成,下载前可以参看下载内容)

下载文件列表

project_fir_test/c1.coe
project_fir_test/c2.coe
project_fir_test/data.coe
project_fir_test/project_fir_test.cache/wt/java_command_handlers.wdf
project_fir_test/project_fir_test.cache/wt/synthesis.wdf
project_fir_test/project_fir_test.cache/wt/synthesis_details.wdf
project_fir_test/project_fir_test.cache/wt/webtalk_pa.xml
project_fir_test/project_fir_test.cache/wt/xsim.wdf
project_fir_test/project_fir_test.hw/project_fir_test.lpr
project_fir_test/project_fir_test.hw/webtalk/.xsim_webtallk.info
project_fir_test/project_fir_test.runs/.jobs/vrs_config_1.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_10.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_11.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_12.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_13.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_14.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_15.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_16.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_17.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_18.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_19.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_2.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_20.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_21.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_22.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_23.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_24.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_25.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_26.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_27.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_28.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_3.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_4.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_5.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_6.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_7.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_8.xml
project_fir_test/project_fir_test.runs/.jobs/vrs_config_9.xml
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/.vivado.begin.rst
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/.vivado.end.rst
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/.Vivado_Synthesis.queue.rst
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/blk_mem_gen_0.dcp
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/blk_mem_gen_0.tcl
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/blk_mem_gen_0.vds
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/blk_mem_gen_0_utilization_synth.pb
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/blk_mem_gen_0_utilization_synth.rpt
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/gen_run.xml
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/htr.txt
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/ISEWrap.js
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/ISEWrap.sh
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/project.wdf
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/rundef.js
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/runme.bat
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/runme.log
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/runme.sh
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/vivado.jou
project_fir_test/project_fir_test.runs/blk_mem_gen_0_synth_1/vivado.pb
project_fir_test/project_fir_test.runs/dds_highf_synth_1/.vivado.begin.rst
project_fir_test/project_fir_test.runs/dds_highf_synth_1/.vivado.end.rst
project_fir_test/project_fir_test.runs/dds_highf_synth_1/.Vivado_Synthesis.queue.rst
project_fir_test/project_fir_test.runs/dds_highf_synth_1/dds_highf.dcp
project_fir_test/project_fir_test.runs/dds_highf_synth_1/dds_highf.tcl
project_fir_test/project_fir_test.runs/dds_highf_synth_1/dds_highf.vds
project_fir_test/project_fir_test.runs/dds_highf_synth_1/dds_highf_utilization_synth.pb
project_fir_test/project_fir_test.runs/dds_highf_synth_1/dds_highf_utilization_synth.rpt
project_fir_test/project_fir_test.runs/dds_highf_synth_1/dont_touch.xdc
project_fir_test/project_fir_test.runs/dds_highf_synth_1/gen_run.xml
project_fir_test/project_fir_test.runs/dds_highf_synth_1/htr.txt
project_fir_test/project_fir_test.runs/dds_highf_synth_1/ISEWrap.js
project_fir_test/project_fir_test.runs/dds_highf_synth_1/ISEWrap.sh
project_fir_test/project_fir_test.runs/dds_highf_synth_1/project.wdf
project_fir_test/project_fir_test.runs/dds_highf_synth_1/rundef.js
project_fir_test/project_fir_test.runs/dds_highf_synth_1/runme.bat
project_fir_test/project_fir_test.runs/dds_highf_synth_1/runme.log
project_fir_test/project_fir_test.runs/dds_highf_synth_1/runme.sh
project_fir_test/project_fir_test.runs/dds_highf_synth_1/vivado.jou
project_fir_test/project_fir_test.runs

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