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文件名称:642_cpld
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- 上传时间:2012-11-15
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文件大小:84.59kb
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开发DM642系统很好用的cpld程序,包含字符叠加部分-DM642 system, well developed procedures for using cpld, including part of the OSD
相关搜索: DM642 CPLD
(系统自动生成,下载前可以参看下载内容)
下载文件列表
642/db/DM642_Verilog.(0).cnf.cdb
642/db/DM642_Verilog.(0).cnf.hdb
642/db/DM642_Verilog.(1).cnf.cdb
642/db/DM642_Verilog.(1).cnf.hdb
642/db/DM642_Verilog.asm.qmsg
642/db/DM642_Verilog.cbx.xml
642/db/DM642_Verilog.cmp.cdb
642/db/DM642_Verilog.cmp.hdb
642/db/DM642_Verilog.cmp.logdb
642/db/DM642_Verilog.cmp.rdb
642/db/DM642_Verilog.cmp.tdb
642/db/DM642_Verilog.cmp0.ddb
642/db/DM642_Verilog.dbp
642/db/DM642_Verilog.db_info
642/db/DM642_Verilog.eco.cdb
642/db/DM642_Verilog.eds_overflow
642/db/DM642_Verilog.fit.qmsg
642/db/DM642_Verilog.fnsim.cdb
642/db/DM642_Verilog.fnsim.hdb
642/db/DM642_Verilog.fnsim.qmsg
642/db/DM642_Verilog.hier_info
642/db/DM642_Verilog.hif
642/db/DM642_Verilog.map.cdb
642/db/DM642_Verilog.map.hdb
642/db/DM642_Verilog.map.logdb
642/db/DM642_Verilog.map.qmsg
642/db/DM642_Verilog.pre_map.cdb
642/db/DM642_Verilog.pre_map.hdb
642/db/DM642_Verilog.psp
642/db/DM642_Verilog.rtlv.hdb
642/db/DM642_Verilog.rtlv_sg.cdb
642/db/DM642_Verilog.rtlv_sg_swap.cdb
642/db/DM642_Verilog.sgdiff.cdb
642/db/DM642_Verilog.sgdiff.hdb
642/db/DM642_Verilog.sim.hdb
642/db/DM642_Verilog.sim.qmsg
642/db/DM642_Verilog.sim.rdb
642/db/DM642_Verilog.sim.vwf
642/db/DM642_Verilog.sld_design_entry.sci
642/db/DM642_Verilog.sld_design_entry_dsc.sci
642/db/DM642_Verilog.syn_hier_info
642/db/DM642_Verilog.tan.qmsg
642/db/wed.zsf
642/DM642_Verilog.asm.rpt
642/DM642_Verilog.bdf
642/DM642_Verilog.done
642/DM642_Verilog.fit.rpt
642/DM642_Verilog.fit.summary
642/DM642_Verilog.flow.rpt
642/DM642_Verilog.map.rpt
642/DM642_Verilog.map.summary
642/DM642_Verilog.pin
642/DM642_Verilog.pof
642/DM642_Verilog.qpf
642/DM642_Verilog.qsf
642/DM642_Verilog.qws
642/DM642_Verilog.sim.rpt
642/DM642_Verilog.tan.rpt
642/DM642_Verilog.vwf
642/mini_sys.v
642/Waveform1.vwf
642/db
642
642/db/DM642_Verilog.(0).cnf.hdb
642/db/DM642_Verilog.(1).cnf.cdb
642/db/DM642_Verilog.(1).cnf.hdb
642/db/DM642_Verilog.asm.qmsg
642/db/DM642_Verilog.cbx.xml
642/db/DM642_Verilog.cmp.cdb
642/db/DM642_Verilog.cmp.hdb
642/db/DM642_Verilog.cmp.logdb
642/db/DM642_Verilog.cmp.rdb
642/db/DM642_Verilog.cmp.tdb
642/db/DM642_Verilog.cmp0.ddb
642/db/DM642_Verilog.dbp
642/db/DM642_Verilog.db_info
642/db/DM642_Verilog.eco.cdb
642/db/DM642_Verilog.eds_overflow
642/db/DM642_Verilog.fit.qmsg
642/db/DM642_Verilog.fnsim.cdb
642/db/DM642_Verilog.fnsim.hdb
642/db/DM642_Verilog.fnsim.qmsg
642/db/DM642_Verilog.hier_info
642/db/DM642_Verilog.hif
642/db/DM642_Verilog.map.cdb
642/db/DM642_Verilog.map.hdb
642/db/DM642_Verilog.map.logdb
642/db/DM642_Verilog.map.qmsg
642/db/DM642_Verilog.pre_map.cdb
642/db/DM642_Verilog.pre_map.hdb
642/db/DM642_Verilog.psp
642/db/DM642_Verilog.rtlv.hdb
642/db/DM642_Verilog.rtlv_sg.cdb
642/db/DM642_Verilog.rtlv_sg_swap.cdb
642/db/DM642_Verilog.sgdiff.cdb
642/db/DM642_Verilog.sgdiff.hdb
642/db/DM642_Verilog.sim.hdb
642/db/DM642_Verilog.sim.qmsg
642/db/DM642_Verilog.sim.rdb
642/db/DM642_Verilog.sim.vwf
642/db/DM642_Verilog.sld_design_entry.sci
642/db/DM642_Verilog.sld_design_entry_dsc.sci
642/db/DM642_Verilog.syn_hier_info
642/db/DM642_Verilog.tan.qmsg
642/db/wed.zsf
642/DM642_Verilog.asm.rpt
642/DM642_Verilog.bdf
642/DM642_Verilog.done
642/DM642_Verilog.fit.rpt
642/DM642_Verilog.fit.summary
642/DM642_Verilog.flow.rpt
642/DM642_Verilog.map.rpt
642/DM642_Verilog.map.summary
642/DM642_Verilog.pin
642/DM642_Verilog.pof
642/DM642_Verilog.qpf
642/DM642_Verilog.qsf
642/DM642_Verilog.qws
642/DM642_Verilog.sim.rpt
642/DM642_Verilog.tan.rpt
642/DM642_Verilog.vwf
642/mini_sys.v
642/Waveform1.vwf
642/db
642
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