- josephus 数据结构实验(循环链表问题) 学会选择合适的数据结构来解决实际问题 学会如何创建一个循环链表在循环链表中如何进行查找在循环链表中如何进行删除
- VB+MapX3 vb+mapxvb+mo二次开发实现鹰眼功能
- LCDS3C2410 S3C2410下LCD驱动程序移植 及GUI程序编写 以一个实例来叙述S3C2410下一个驱动程序的编写(本文的初始化源码以华恒公司提供的s3c2410fb.c为基础)及简单的GUI程序的编写
- Josephus 算法
- PspanDrv powerspan pci slave device driver
- 8051 51单片机的c语言开发 这是一本书 里面有十五章 主要讲单片机的c语言开发 里面有丰富的例子 源代码均通过了调试
文件名称:1_LAB
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:5.84mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
相关搜索: shift
(系统自动生成,下载前可以参看下载内容)
下载文件列表
1_LAB/DESPREAD.fsdb
1_LAB/DESPREAD.v
1_LAB/INCA_libs/.ncv.lock
1_LAB/INCA_libs/cds.lib
1_LAB/INCA_libs/hdl.var
1_LAB/INCA_libs/snap.lnx86.nc/.elab.args
1_LAB/INCA_libs/snap.lnx86.nc/.hard.args
1_LAB/INCA_libs/snap.lnx86.nc/.ncv.lock
1_LAB/INCA_libs/snap.lnx86.nc/bind.lst.lnx86
1_LAB/INCA_libs/snap.lnx86.nc/cds.lib
1_LAB/INCA_libs/snap.lnx86.nc/hdl.var
1_LAB/INCA_libs/worklib/.cdsvmod
1_LAB/INCA_libs/worklib/.inca.db.163.lnx86
1_LAB/INCA_libs/worklib/cdsinfo.tag
1_LAB/INCA_libs/worklib/inca.lnx86.163.pak
1_LAB/ncverilog.log
1_LAB/PATTERN.v
1_LAB/TESTBED.v
1_LAB/INCA_libs/snap.lnx86.nc
1_LAB/INCA_libs/worklib
1_LAB/INCA_libs
1_LAB
1_LAB/DESPREAD.v
1_LAB/INCA_libs/.ncv.lock
1_LAB/INCA_libs/cds.lib
1_LAB/INCA_libs/hdl.var
1_LAB/INCA_libs/snap.lnx86.nc/.elab.args
1_LAB/INCA_libs/snap.lnx86.nc/.hard.args
1_LAB/INCA_libs/snap.lnx86.nc/.ncv.lock
1_LAB/INCA_libs/snap.lnx86.nc/bind.lst.lnx86
1_LAB/INCA_libs/snap.lnx86.nc/cds.lib
1_LAB/INCA_libs/snap.lnx86.nc/hdl.var
1_LAB/INCA_libs/worklib/.cdsvmod
1_LAB/INCA_libs/worklib/.inca.db.163.lnx86
1_LAB/INCA_libs/worklib/cdsinfo.tag
1_LAB/INCA_libs/worklib/inca.lnx86.163.pak
1_LAB/ncverilog.log
1_LAB/PATTERN.v
1_LAB/TESTBED.v
1_LAB/INCA_libs/snap.lnx86.nc
1_LAB/INCA_libs/worklib
1_LAB/INCA_libs
1_LAB
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.