文件名称:74hc138
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- 上传时间:2012-11-16
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文件大小:341.97kb
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74ls138 基于verilog语言的实现 -Verilog language 74ls138 based on the realization of
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下载文件列表
74hc138.pdf
74hc138/
74hc138/74hc138.prj
74hc138/component/
74hc138/constraint/
74hc138/coreconsole/
74hc138/designer/
74hc138/designer/impl1/
74hc138/designer/impl1/decoder_38.adb
74hc138/designer/impl1/decoder_38.dtf/
74hc138/designer/impl1/decoder_38.dtf/verify.log
74hc138/designer/impl1/decoder_38.ide_des
74hc138/designer/impl1/decoder_38.pdb
74hc138/designer/impl1/decoder_38.pdb.depends
74hc138/designer/impl1/decoder_38.tcl
74hc138/designer/impl1/decoder_38_ba.sdf
74hc138/designer/impl1/decoder_38_ba.v
74hc138/designer/impl1/designer.log
74hc138/designer/impl1/simulation/
74hc138/hdl/
74hc138/hdl/74hc138.v
74hc138/phy_synthesis/
74hc138/simulation/
74hc138/simulation/modelsim.ini
74hc138/simulation/modelsim.ini.sav
74hc138/simulation/modelsim.log
74hc138/simulation/presynth/
74hc138/simulation/presynth/decoder_38/
74hc138/simulation/presynth/decoder_38/verilog.psm
74hc138/simulation/presynth/decoder_38/_primary.dat
74hc138/simulation/presynth/decoder_38/_primary.dbs
74hc138/simulation/presynth/decoder_38/_primary.vhd
74hc138/simulation/presynth/testbench/
74hc138/simulation/presynth/testbench/verilog.psm
74hc138/simulation/presynth/testbench/_primary.dat
74hc138/simulation/presynth/testbench/_primary.dbs
74hc138/simulation/presynth/testbench/_primary.vhd
74hc138/simulation/presynth/_info
74hc138/simulation/presynth/_temp/
74hc138/simulation/presynth/_temp/vlogzyq214
74hc138/simulation/run.do
74hc138/simulation/vsim.wlf
74hc138/smartgen/
74hc138/smartgen/smartgen.aws
74hc138/stimulus/
74hc138/stimulus/testbench.v
74hc138/synthesis/
74hc138/synthesis/backup/
74hc138/synthesis/backup/decoder_38.srr
74hc138/synthesis/coreip/
74hc138/synthesis/decoder_38.areasrr
74hc138/synthesis/decoder_38.edn
74hc138/synthesis/decoder_38.fse
74hc138/synthesis/decoder_38.htm
74hc138/synthesis/decoder_38.map
74hc138/synthesis/decoder_38.pdc
74hc138/synthesis/decoder_38.sap
74hc138/synthesis/decoder_38.sdf
74hc138/synthesis/decoder_38.so
74hc138/synthesis/decoder_38.srd
74hc138/synthesis/decoder_38.srm
74hc138/synthesis/decoder_38.srr
74hc138/synthesis/decoder_38.srs
74hc138/synthesis/decoder_38.szr
74hc138/synthesis/decoder_38.tlg
74hc138/synthesis/decoder_38_sdc.sdc
74hc138/synthesis/decoder_38_syn.prj
74hc138/synthesis/run_options.txt
74hc138/synthesis/stdout.log
74hc138/synthesis/syntmp/
74hc138/synthesis/syntmp/decoder_38.plg
74hc138/synthesis/syntmp/decoder_38_flink.htm
74hc138/synthesis/syntmp/decoder_38_srr.htm
74hc138/synthesis/syntmp/decoder_38_toc.htm
74hc138/synthesis/syntmp/sap.log
74hc138/viewdraw/
74hc138/viewdraw/sch/
74hc138/viewdraw/sym/
74hc138/viewdraw/vf/
74hc138/viewdraw/vf/project.lst
74hc138/viewdraw/viewdraw.ini
74hc138/viewdraw/wir/
74hc138/
74hc138/74hc138.prj
74hc138/component/
74hc138/constraint/
74hc138/coreconsole/
74hc138/designer/
74hc138/designer/impl1/
74hc138/designer/impl1/decoder_38.adb
74hc138/designer/impl1/decoder_38.dtf/
74hc138/designer/impl1/decoder_38.dtf/verify.log
74hc138/designer/impl1/decoder_38.ide_des
74hc138/designer/impl1/decoder_38.pdb
74hc138/designer/impl1/decoder_38.pdb.depends
74hc138/designer/impl1/decoder_38.tcl
74hc138/designer/impl1/decoder_38_ba.sdf
74hc138/designer/impl1/decoder_38_ba.v
74hc138/designer/impl1/designer.log
74hc138/designer/impl1/simulation/
74hc138/hdl/
74hc138/hdl/74hc138.v
74hc138/phy_synthesis/
74hc138/simulation/
74hc138/simulation/modelsim.ini
74hc138/simulation/modelsim.ini.sav
74hc138/simulation/modelsim.log
74hc138/simulation/presynth/
74hc138/simulation/presynth/decoder_38/
74hc138/simulation/presynth/decoder_38/verilog.psm
74hc138/simulation/presynth/decoder_38/_primary.dat
74hc138/simulation/presynth/decoder_38/_primary.dbs
74hc138/simulation/presynth/decoder_38/_primary.vhd
74hc138/simulation/presynth/testbench/
74hc138/simulation/presynth/testbench/verilog.psm
74hc138/simulation/presynth/testbench/_primary.dat
74hc138/simulation/presynth/testbench/_primary.dbs
74hc138/simulation/presynth/testbench/_primary.vhd
74hc138/simulation/presynth/_info
74hc138/simulation/presynth/_temp/
74hc138/simulation/presynth/_temp/vlogzyq214
74hc138/simulation/run.do
74hc138/simulation/vsim.wlf
74hc138/smartgen/
74hc138/smartgen/smartgen.aws
74hc138/stimulus/
74hc138/stimulus/testbench.v
74hc138/synthesis/
74hc138/synthesis/backup/
74hc138/synthesis/backup/decoder_38.srr
74hc138/synthesis/coreip/
74hc138/synthesis/decoder_38.areasrr
74hc138/synthesis/decoder_38.edn
74hc138/synthesis/decoder_38.fse
74hc138/synthesis/decoder_38.htm
74hc138/synthesis/decoder_38.map
74hc138/synthesis/decoder_38.pdc
74hc138/synthesis/decoder_38.sap
74hc138/synthesis/decoder_38.sdf
74hc138/synthesis/decoder_38.so
74hc138/synthesis/decoder_38.srd
74hc138/synthesis/decoder_38.srm
74hc138/synthesis/decoder_38.srr
74hc138/synthesis/decoder_38.srs
74hc138/synthesis/decoder_38.szr
74hc138/synthesis/decoder_38.tlg
74hc138/synthesis/decoder_38_sdc.sdc
74hc138/synthesis/decoder_38_syn.prj
74hc138/synthesis/run_options.txt
74hc138/synthesis/stdout.log
74hc138/synthesis/syntmp/
74hc138/synthesis/syntmp/decoder_38.plg
74hc138/synthesis/syntmp/decoder_38_flink.htm
74hc138/synthesis/syntmp/decoder_38_srr.htm
74hc138/synthesis/syntmp/decoder_38_toc.htm
74hc138/synthesis/syntmp/sap.log
74hc138/viewdraw/
74hc138/viewdraw/sch/
74hc138/viewdraw/sym/
74hc138/viewdraw/vf/
74hc138/viewdraw/vf/project.lst
74hc138/viewdraw/viewdraw.ini
74hc138/viewdraw/wir/
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