文件名称:RD1011_rev01.2
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- 上传时间:2012-11-16
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文件大小:212.49kb
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介绍说明--下载内容来自于网络,使用问题请自行百度
采用VHDL实现的UART硬件模块,该模块包括了modem的硬件实现,已经仿真测试代码,顶层模块可以采用VHDL或verilog实现,便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog to achieve easy embedded into the design of their own. Document with detailed instructions and notes.
相关搜索: Verilog modem
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下载文件列表
.metadata/
RD1011/
RD1011/docs/
RD1011/docs/RD1011.pdf
RD1011/docs/rd1011_readme.txt
RD1011/project/
RD1011/project/4KZE/
RD1011/project/4KZE/UART_4K.lci
RD1011/project/4KZE/UART_4K.syn
RD1011/project/4KZE/uart_int_tb_vhda.udo
RD1011/project/4KZE/uart_int_tb_vhdaf.udo
RD1011/project/4KZE/uart_rx_tb_vhda.udo
RD1011/project/4KZE/uart_rx_tb_vhdaf.udo
RD1011/project/4KZE/uart_tx_tb_vhda.udo
RD1011/project/4KZE/uart_tx_tb_vhdaf.udo
RD1011/project/XO/
RD1011/project/XO/uart.lpf
RD1011/project/XO/UART.syn
RD1011/project/XO/uart_int_tb_vhdf.udo
RD1011/project/XO/uart_int_tb_vhdr.udo
RD1011/project/XO/uart_rx_tb_vhdf.udo
RD1011/project/XO/uart_rx_tb_vhdr.udo
RD1011/project/XO/uart_tx_tb_vhdf.udo
RD1011/project/XO/uart_tx_tb_vhdr.udo
RD1011/source/
RD1011/source/intface.vhd
RD1011/source/modem.vhd
RD1011/source/rxcver.vhd
RD1011/source/txmitt.vhd
RD1011/source/uart_top.vhd
RD1011/source/UART_VerilogWrapper_TOP.v
RD1011/testbench/
RD1011/testbench/uart_int_tb.vhd
RD1011/testbench/uart_rx_tb.vhd
RD1011/testbench/uart_tx_tb.vhd
RD1011/
RD1011/docs/
RD1011/docs/RD1011.pdf
RD1011/docs/rd1011_readme.txt
RD1011/project/
RD1011/project/4KZE/
RD1011/project/4KZE/UART_4K.lci
RD1011/project/4KZE/UART_4K.syn
RD1011/project/4KZE/uart_int_tb_vhda.udo
RD1011/project/4KZE/uart_int_tb_vhdaf.udo
RD1011/project/4KZE/uart_rx_tb_vhda.udo
RD1011/project/4KZE/uart_rx_tb_vhdaf.udo
RD1011/project/4KZE/uart_tx_tb_vhda.udo
RD1011/project/4KZE/uart_tx_tb_vhdaf.udo
RD1011/project/XO/
RD1011/project/XO/uart.lpf
RD1011/project/XO/UART.syn
RD1011/project/XO/uart_int_tb_vhdf.udo
RD1011/project/XO/uart_int_tb_vhdr.udo
RD1011/project/XO/uart_rx_tb_vhdf.udo
RD1011/project/XO/uart_rx_tb_vhdr.udo
RD1011/project/XO/uart_tx_tb_vhdf.udo
RD1011/project/XO/uart_tx_tb_vhdr.udo
RD1011/source/
RD1011/source/intface.vhd
RD1011/source/modem.vhd
RD1011/source/rxcver.vhd
RD1011/source/txmitt.vhd
RD1011/source/uart_top.vhd
RD1011/source/UART_VerilogWrapper_TOP.v
RD1011/testbench/
RD1011/testbench/uart_int_tb.vhd
RD1011/testbench/uart_rx_tb.vhd
RD1011/testbench/uart_tx_tb.vhd
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