文件名称:min
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- 上传时间:2012-11-16
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文件大小:1.3mb
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verilog编写的基于并行流水线结构的16阶滤波器的实现-filter
相关搜索: min Filter
verilog
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下载文件列表
modelsim/222.BMP
modelsim/add.v
modelsim/add.v.bak
modelsim/afternoon.cr.mti
modelsim/afternoon.mpf
modelsim/clk.v
modelsim/clk.v.bak
modelsim/inputshift.v
modelsim/ISE/ise/add.v
modelsim/ISE/ise/clk.spl
modelsim/ISE/ise/clk.sym
modelsim/ISE/ise/clk.v
modelsim/ISE/ise/clk.vhi
modelsim/ISE/ise/inputshift.v
modelsim/ISE/ise/ise.ise
modelsim/ISE/ise/ise.ise_ISE_Backup
modelsim/ISE/ise/ise.ntrc_log
modelsim/ISE/ise/lut.v
modelsim/ISE/ise/mul.v
modelsim/ISE/ise/out.v
modelsim/ISE/ise/outputadd.v
modelsim/ISE/ise/outputshift.v
modelsim/ISE/ise/ram.patt
modelsim/ISE/ise/ramh.patt
modelsim/ISE/ise/test_top.fdo
modelsim/ISE/ise/test_top.udo
modelsim/ISE/ise/test_top.v
modelsim/ISE/ise/top.cmd_log
modelsim/ISE/ise/top.lso
modelsim/ISE/ise/top.ngc
modelsim/ISE/ise/top.ngr
modelsim/ISE/ise/top.prj
modelsim/ISE/ise/top.stx
modelsim/ISE/ise/top.syr
modelsim/ISE/ise/top.v
modelsim/ISE/ise/top.xst
modelsim/ISE/ise/top_summary.html
modelsim/ISE/ise/transcript
modelsim/ISE/ise/vsim.wlf
modelsim/ISE/ise/work/add/verilog.asm
modelsim/ISE/ise/work/add/_primary.dat
modelsim/ISE/ise/work/add/_primary.vhd
modelsim/ISE/ise/work/clk/verilog.asm
modelsim/ISE/ise/work/clk/_primary.dat
modelsim/ISE/ise/work/clk/_primary.vhd
modelsim/ISE/ise/work/glbl/verilog.asm
modelsim/ISE/ise/work/glbl/_primary.dat
modelsim/ISE/ise/work/glbl/_primary.vhd
modelsim/ISE/ise/work/inputshift/verilog.asm
modelsim/ISE/ise/work/inputshift/_primary.dat
modelsim/ISE/ise/work/inputshift/_primary.vhd
modelsim/ISE/ise/work/lut/verilog.asm
modelsim/ISE/ise/work/lut/_primary.dat
modelsim/ISE/ise/work/lut/_primary.vhd
modelsim/ISE/ise/work/mul/verilog.asm
modelsim/ISE/ise/work/mul/_primary.dat
modelsim/ISE/ise/work/mul/_primary.vhd
modelsim/ISE/ise/work/out/verilog.asm
modelsim/ISE/ise/work/out/_primary.dat
modelsim/ISE/ise/work/out/_primary.vhd
modelsim/ISE/ise/work/outputadd/verilog.asm
modelsim/ISE/ise/work/outputadd/_primary.dat
modelsim/ISE/ise/work/outputadd/_primary.vhd
modelsim/ISE/ise/work/outputshift/verilog.asm
modelsim/ISE/ise/work/outputshift/_primary.dat
modelsim/ISE/ise/work/outputshift/_primary.vhd
modelsim/ISE/ise/work/test_top/verilog.asm
modelsim/ISE/ise/work/test_top/_primary.dat
modelsim/ISE/ise/work/test_top/_primary.vhd
modelsim/ISE/ise/work/top/verilog.asm
modelsim/ISE/ise/work/top/_primary.dat
modelsim/ISE/ise/work/top/_primary.vhd
modelsim/ISE/ise/work/_info
modelsim/ISE/ise/xst/dump.xst/top.prj/ntrc.scr
modelsim/ISE/ise/xst/work/hdllib.ref
modelsim/ISE/ise/xst/work/vlg14/out.bin
modelsim/ISE/ise/xst/work/vlg23/outputshift.bin
modelsim/ISE/ise/xst/work/vlg2A/inputshift.bin
modelsim/ISE/ise/xst/work/vlg32/clk.bin
modelsim/ISE/ise/xst/work/vlg49/lut.bin
modelsim/ISE/ise/xst/work/vlg51/add.bin
modelsim/ISE/ise/xst/work/vlg5A/mul.bin
modelsim/ISE/ise/xst/work/vlg6F/top.bin
modelsim/ISE/ise/xst/work/vlg7E/outputadd.bin
modelsim/ISE/ise/_xmsgs/xst.xmsgs
modelsim/lut.v
modelsim/modelsim.ise
modelsim/modelsim.ntrc_log
modelsim/modelsim.restore
modelsim/mul.v
modelsim/mul.v.bak
modelsim/out.v
modelsim/out.v.bak
modelsim/outputadd.v
modelsim/outputadd.v.bak
modelsim/outputshift.v
modelsim/outputshift.v.bak
modelsim/ram.patt
modelsim/ramh.patt
modelsim/Snap1.bmp
modelsim/test_top.fdo
modelsim/test_top.udo
modelsim/test_top.v
modelsim/test_top.v.bak
modelsim/test_top_wave.fdo
modelsim/top.bmp
modelsim/top.cmd_log
modelsim/top.lso
modelsim/top.ngc
modelsim/top.ngr
modelsim/top.prj
modelsim/top.stx
modelsim/top.syr
modelsim/top.udo
modelsim/top.v
modelsim/top.v.bak
modelsim/top.xst
modelsim/top_summary.html
modelsim/top_wave.fdo
modelsim/top_xst.xrpt
modelsim/transcript
modelsim/vsim.wlf
modelsim/work/add/verilog.asm
modelsim/work/add/_primary.dat
modelsim/work/add/_primary.vhd
modelsim/work/clk/verilog.asm
modelsim/work/clk/_primary.dat
modelsim/work/clk/_primary.vhd
modelsim/work/glbl/verilog.asm
modelsim/work/glbl/_primary.dat
modelsim/work/glbl/_primary.vhd
modelsim/work/inputshift/verilog.asm
modelsim/work/inputshift/_primary.dat
modelsim/work/inputshift/_primary.vhd
modelsim/work/lut/verilog.asm
modelsim/work/lut/_primary.dat
modelsim/work/lut/_primary.vhd
modelsim/work/mul/verilog.asm
modelsim/work/mul/_primary.dat
modelsim/work/mul/_primary.vhd
modelsim/work/out/verilog.asm
modelsim/work/out/_primary.dat
modelsim/work/out/_primary.vhd
modelsim/work/outputadd/verilog.asm
modelsim/work/outputadd/_primary.dat
modelsim/work/outputadd/_primary.vhd
modelsim/work/outputshift/verilog.asm
modelsim/work/outputshift/_primary.dat
modelsim/work/outputshift/_primary.vhd
modelsim/work/test_top/transcript
modelsim/work/test_top/verilog.asm
modelsim/work/test_top/_primary.dat
modelsim/work/test_top/_primary.vhd
modelsim/work/top/verilog.asm
modelsim/work/top/_primary.dat
modelsim/work/top/_primary.vhd
modelsim/work/_info
modelsim/xst/dump.xst/top.prj/ntrc.scr
modelsim/xst/work/hdllib.ref
modelsim/xst/work/vlg14/out.bin
modelsim/xst/work/vlg23/outputshift.bin
modelsim/xst/work/vlg2A/inputshift.bin
modelsim/xst/work/vlg32/clk.bin
modelsim/xst/work/vlg49/lut.bin
modelsim/xst/work/vlg51/add.bin
modelsim/xst/work/vlg5A/mul.bin
modelsim/xst/work/vlg6F/top.bin
modelsim/xst/work/vlg7E/ou
modelsim/add.v
modelsim/add.v.bak
modelsim/afternoon.cr.mti
modelsim/afternoon.mpf
modelsim/clk.v
modelsim/clk.v.bak
modelsim/inputshift.v
modelsim/ISE/ise/add.v
modelsim/ISE/ise/clk.spl
modelsim/ISE/ise/clk.sym
modelsim/ISE/ise/clk.v
modelsim/ISE/ise/clk.vhi
modelsim/ISE/ise/inputshift.v
modelsim/ISE/ise/ise.ise
modelsim/ISE/ise/ise.ise_ISE_Backup
modelsim/ISE/ise/ise.ntrc_log
modelsim/ISE/ise/lut.v
modelsim/ISE/ise/mul.v
modelsim/ISE/ise/out.v
modelsim/ISE/ise/outputadd.v
modelsim/ISE/ise/outputshift.v
modelsim/ISE/ise/ram.patt
modelsim/ISE/ise/ramh.patt
modelsim/ISE/ise/test_top.fdo
modelsim/ISE/ise/test_top.udo
modelsim/ISE/ise/test_top.v
modelsim/ISE/ise/top.cmd_log
modelsim/ISE/ise/top.lso
modelsim/ISE/ise/top.ngc
modelsim/ISE/ise/top.ngr
modelsim/ISE/ise/top.prj
modelsim/ISE/ise/top.stx
modelsim/ISE/ise/top.syr
modelsim/ISE/ise/top.v
modelsim/ISE/ise/top.xst
modelsim/ISE/ise/top_summary.html
modelsim/ISE/ise/transcript
modelsim/ISE/ise/vsim.wlf
modelsim/ISE/ise/work/add/verilog.asm
modelsim/ISE/ise/work/add/_primary.dat
modelsim/ISE/ise/work/add/_primary.vhd
modelsim/ISE/ise/work/clk/verilog.asm
modelsim/ISE/ise/work/clk/_primary.dat
modelsim/ISE/ise/work/clk/_primary.vhd
modelsim/ISE/ise/work/glbl/verilog.asm
modelsim/ISE/ise/work/glbl/_primary.dat
modelsim/ISE/ise/work/glbl/_primary.vhd
modelsim/ISE/ise/work/inputshift/verilog.asm
modelsim/ISE/ise/work/inputshift/_primary.dat
modelsim/ISE/ise/work/inputshift/_primary.vhd
modelsim/ISE/ise/work/lut/verilog.asm
modelsim/ISE/ise/work/lut/_primary.dat
modelsim/ISE/ise/work/lut/_primary.vhd
modelsim/ISE/ise/work/mul/verilog.asm
modelsim/ISE/ise/work/mul/_primary.dat
modelsim/ISE/ise/work/mul/_primary.vhd
modelsim/ISE/ise/work/out/verilog.asm
modelsim/ISE/ise/work/out/_primary.dat
modelsim/ISE/ise/work/out/_primary.vhd
modelsim/ISE/ise/work/outputadd/verilog.asm
modelsim/ISE/ise/work/outputadd/_primary.dat
modelsim/ISE/ise/work/outputadd/_primary.vhd
modelsim/ISE/ise/work/outputshift/verilog.asm
modelsim/ISE/ise/work/outputshift/_primary.dat
modelsim/ISE/ise/work/outputshift/_primary.vhd
modelsim/ISE/ise/work/test_top/verilog.asm
modelsim/ISE/ise/work/test_top/_primary.dat
modelsim/ISE/ise/work/test_top/_primary.vhd
modelsim/ISE/ise/work/top/verilog.asm
modelsim/ISE/ise/work/top/_primary.dat
modelsim/ISE/ise/work/top/_primary.vhd
modelsim/ISE/ise/work/_info
modelsim/ISE/ise/xst/dump.xst/top.prj/ntrc.scr
modelsim/ISE/ise/xst/work/hdllib.ref
modelsim/ISE/ise/xst/work/vlg14/out.bin
modelsim/ISE/ise/xst/work/vlg23/outputshift.bin
modelsim/ISE/ise/xst/work/vlg2A/inputshift.bin
modelsim/ISE/ise/xst/work/vlg32/clk.bin
modelsim/ISE/ise/xst/work/vlg49/lut.bin
modelsim/ISE/ise/xst/work/vlg51/add.bin
modelsim/ISE/ise/xst/work/vlg5A/mul.bin
modelsim/ISE/ise/xst/work/vlg6F/top.bin
modelsim/ISE/ise/xst/work/vlg7E/outputadd.bin
modelsim/ISE/ise/_xmsgs/xst.xmsgs
modelsim/lut.v
modelsim/modelsim.ise
modelsim/modelsim.ntrc_log
modelsim/modelsim.restore
modelsim/mul.v
modelsim/mul.v.bak
modelsim/out.v
modelsim/out.v.bak
modelsim/outputadd.v
modelsim/outputadd.v.bak
modelsim/outputshift.v
modelsim/outputshift.v.bak
modelsim/ram.patt
modelsim/ramh.patt
modelsim/Snap1.bmp
modelsim/test_top.fdo
modelsim/test_top.udo
modelsim/test_top.v
modelsim/test_top.v.bak
modelsim/test_top_wave.fdo
modelsim/top.bmp
modelsim/top.cmd_log
modelsim/top.lso
modelsim/top.ngc
modelsim/top.ngr
modelsim/top.prj
modelsim/top.stx
modelsim/top.syr
modelsim/top.udo
modelsim/top.v
modelsim/top.v.bak
modelsim/top.xst
modelsim/top_summary.html
modelsim/top_wave.fdo
modelsim/top_xst.xrpt
modelsim/transcript
modelsim/vsim.wlf
modelsim/work/add/verilog.asm
modelsim/work/add/_primary.dat
modelsim/work/add/_primary.vhd
modelsim/work/clk/verilog.asm
modelsim/work/clk/_primary.dat
modelsim/work/clk/_primary.vhd
modelsim/work/glbl/verilog.asm
modelsim/work/glbl/_primary.dat
modelsim/work/glbl/_primary.vhd
modelsim/work/inputshift/verilog.asm
modelsim/work/inputshift/_primary.dat
modelsim/work/inputshift/_primary.vhd
modelsim/work/lut/verilog.asm
modelsim/work/lut/_primary.dat
modelsim/work/lut/_primary.vhd
modelsim/work/mul/verilog.asm
modelsim/work/mul/_primary.dat
modelsim/work/mul/_primary.vhd
modelsim/work/out/verilog.asm
modelsim/work/out/_primary.dat
modelsim/work/out/_primary.vhd
modelsim/work/outputadd/verilog.asm
modelsim/work/outputadd/_primary.dat
modelsim/work/outputadd/_primary.vhd
modelsim/work/outputshift/verilog.asm
modelsim/work/outputshift/_primary.dat
modelsim/work/outputshift/_primary.vhd
modelsim/work/test_top/transcript
modelsim/work/test_top/verilog.asm
modelsim/work/test_top/_primary.dat
modelsim/work/test_top/_primary.vhd
modelsim/work/top/verilog.asm
modelsim/work/top/_primary.dat
modelsim/work/top/_primary.vhd
modelsim/work/_info
modelsim/xst/dump.xst/top.prj/ntrc.scr
modelsim/xst/work/hdllib.ref
modelsim/xst/work/vlg14/out.bin
modelsim/xst/work/vlg23/outputshift.bin
modelsim/xst/work/vlg2A/inputshift.bin
modelsim/xst/work/vlg32/clk.bin
modelsim/xst/work/vlg49/lut.bin
modelsim/xst/work/vlg51/add.bin
modelsim/xst/work/vlg5A/mul.bin
modelsim/xst/work/vlg6F/top.bin
modelsim/xst/work/vlg7E/ou
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