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文件名称:fir

  • 所属分类：
    Windows Develop
  • 标签属性：
    [Matlab] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.55mb
  • 已下载：
    0次
  • 提 供 者：
    l*****
  • 相关连接：
    无
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修正介绍说明

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fir 滤波器 Systems generator 实现并转化为verilog语言-fir Filter Systems generator to achieve and into verilog language
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fir/coefficients.fda
fir/fir.err
fir/fir.mdl
fir/fir_sysgen.log
fir/fir_sysgen_error.log
fir/netlist/distributed_arithmetic_fir_filter_spartan3_9_0_1a9102dd9ea9946b.edn
fir/netlist/distributed_arithmetic_fir_filter_spartan3_9_0_1a9102dd9ea9946b.mif
fir/netlist/fir.v
fir/netlist/fir.vhd
fir/netlist/fir_cw.bit
fir/netlist/fir_cw.hwc
fir/netlist/fir_cw.ise
fir/netlist/fir_cw.sdc
fir/netlist/fir_cw.sgp
fir/netlist/fir_cw.ucf
fir/netlist/fir_cw.v
fir/netlist/fir_cw.vhd
fir/netlist/fir_cw.xcf
fir/netlist/fir_hwcosim_lib.mdl
fir/netlist/globals
fir/netlist/hdlFiles
fir/netlist/jtagcosim_top.ucf
fir/netlist/jtagcosim_top.vhd
fir/netlist/name_translations
fir/netlist/synopsis
fir/netlist/synth_model/commandLines
fir/netlist/synth_model/fir.results
fir/netlist/synth_model/fir.v
fir/netlist/synth_model/fir_cw.ise
fir/netlist/synth_model/fir_cw.lso
fir/netlist/synth_model/fir_cw.ngc
fir/netlist/synth_model/fir_cw.ngc_xst.xrpt
fir/netlist/synth_model/fir_cw.sdc
fir/netlist/synth_model/fir_cw.sgp
fir/netlist/synth_model/fir_cw.v
fir/netlist/synth_model/fir_cw.xcf
fir/netlist/synth_model/globals
fir/netlist/synth_model/hdlFiles
fir/netlist/synth_model/synopsis
fir/netlist/synth_model/vcom.do
fir/netlist/synth_model/xlfir_1ch_distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad13eef.ngc
fir/netlist/synth_model/xlnx_auto_0.ise
fir/netlist/synth_model/xlpersistentdff.ngc
fir/netlist/synth_model/xst/work/hdllib.ref
fir/netlist/synth_model/xst/work/vlg01/xlfir__1ch__distributed__arithmetic__fir__filter__spartan3e__9__0__153c552e401ddad13eef.bin
fir/netlist/synth_model/xst/work/vlg03/cast.bin
fir/netlist/synth_model/xst/work/vlg07/synth__reg.bin
fir/netlist/synth_model/xst/work/vlg10/xlclockdriver.bin
fir/netlist/synth_model/xst/work/vlg13/default__clock__driver.bin
fir/netlist/synth_model/xst/work/vlg14/round__towards__even.bin
fir/netlist/synth_model/xst/work/vlg1E/align__input.bin
fir/netlist/synth_model/xst/work/vlg1E/srl17e.bin
fir/netlist/synth_model/xst/work/vlg21/xlconvert.bin
fir/netlist/synth_model/xst/work/vlg24/single__reg__w__init.bin
fir/netlist/synth_model/xst/work/vlg24/zero__ext.bin
fir/netlist/synth_model/xst/work/vlg28/synth__reg__w__init.bin
fir/netlist/synth_model/xst/work/vlg2B/round__towards__inf.bin
fir/netlist/synth_model/xst/work/vlg35/wrap__arith.bin
fir/netlist/synth_model/xst/work/vlg39/pad__lsb.bin
fir/netlist/synth_model/xst/work/vlg4A/convert__type.bin
fir/netlist/synth_model/xst/work/vlg4D/xlpersistentdff.bin
fir/netlist/synth_model/xst/work/vlg4E/fir__cw.bin
fir/netlist/synth_model/xst/work/vlg54/trunc.bin
fir/netlist/synth_model/xst/work/vlg55/extend__msb.bin
fir/netlist/synth_model/xst/work/vlg55/sign__ext.bin
fir/netlist/synth_model/xst/work/vlg5E/xlclkprobe.bin
fir/netlist/synth_model/xst/work/vlg6D/saturation__arith.bin
fir/netlist/synth_model/xst/work/vlg73/xldelay.bin
fir/netlist/synth_model/xst/work/vlg75/fir.bin
fir/netlist/synth_model/xst/work/vlg7C/synth__reg__reg.bin
fir/netlist/synth_model/xst_fir.prj
fir/netlist/synth_model/xst_fir.scr
fir/netlist/synth_wrapper/jtagcosim_top.ngc
fir/netlist/synth_wrapper/jtagcosim_top.vhd
fir/netlist/synth_wrapper/xst_jtagcosim_top.prj
fir/netlist/synth_wrapper/xst_jtagcosim_top.scr
fir/netlist/sysgen/commandLines
fir/netlist/sysgen/consolidate.log
fir/netlist/sysgen/fir.v
fir/netlist/sysgen/fir_cw.ise
fir/netlist/sysgen/fir_cw.restore
fir/netlist/sysgen/fir_cw.sdc
fir/netlist/sysgen/fir_cw.sgp
fir/netlist/sysgen/fir_cw.ucf
fir/netlist/sysgen/fir_cw.v
fir/netlist/sysgen/fir_cw.xcf
fir/netlist/sysgen/fir_cw_import.log
fir/netlist/sysgen/fir_cw_import.tcl
fir/netlist/sysgen/globals
fir/netlist/sysgen/hdlFiles
fir/netlist/sysgen/masterScript38632.pl
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.edn
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.mif
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.v
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.veo
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.vhd
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.vho
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.xco
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1_flist.txt
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/coregen_tmp/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1_xmdf.tcl
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.edn
fir/netlist/sysgen/ngc_verilog_TZdL/coregen_AAAY/distributed_arithmetic_fir_filter_spartan3e_9_0_153c552e401ddad1.mif
fir/netlist/sysgen/n

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