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costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Verilog_module
- Verilog编写基于FPGA的鉴相器模块-Write Verilog FPGA-based phase detector module
10010
- Verilog状态机设计-10010序列检测器-Verilog state machine design-10010 Sequence Detector
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
check
- 用Verilog实现的序列检测器，可以检测出任意规定序列-Verilog implementation using the sequence detector
chA
- phase frequency detector verilog
sequencedetector
- verilog code for 3 bit sequence detector
synchronisation
- This circuit is a nice edge detector that gives you synchronous notification of edges on your input signal. There s no excuse for not doing this it s a tiny circuit in just five lines of Verilog.-This circuit is a nice edge detector that gives yo
seqdet
- 串行序列检测器，以得到modelsim仿真波形，用verilog编写。-Serial sequence detector to get modelsim simulation waveform, prepared with verilog.
cordic_atan
- 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated usin
seqdetector1001.v.tar
- 1001 sequence detector in verilog code for mealy state machine
top_module
- OFDM Gaurd Detector, Symbol length = 1024 & Gaurad Length = 256, and test bench written in verilog!
detector
- this file is detector verilog source and test bench file thank you!
10101-sequence-detector
- 课程设计之10101序列检测器的Verilog 实现-10101 sequence detector
Verilog-Code
- Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
verilog-example
- verilog基础实验，包括篮球计数器，序列检测计等-verilog based experiments, including basketball counter sequence detector
10010sequece-detector
- 序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-Sequence generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
sequential detector
- verilog 固定序列检测器，能够检测10111序列，波形无误。适合Verilog初学者学习(Verilog fixed sequence detector)
sequence detector
- sequence detector in verilog for xilinx
verilog状态机
- 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, b