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counter
- 用C++编写的计数器CGI程序，功能强大，运行速度快速可靠，计数器也可以隐藏，该CGI程序运行于WinNT/Intel平台-prepared by the Counter CGI program, a powerful, fast and reliable operating speed, counter can hide, The CGI program runs on WinNT / Intel platform
counter
- Counter in Matlab we can create a counter on matlab with this program
counter
- 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
counter
- 6位数显频率计数器的proteus仿真电路及C语言程序设计，单片机仿真实例-6-digit frequency counter of proteus was circuit simulation and C language programming, microcontroller simulation
counter
- 相信很多人都可以做得一个计数器的程序,不论是用C#、VB、VC++等编程工具。在这里我所做的这个计数器是使用C#做的，效果可能可其他人所做的不一样。它主要的目的是通过等额还贷对买房子的客户分期付款的金额和要多少年限才能还清钱进行计算。-I believe many people could do a counter procedures, whether they are using C#, VB, VC++ And other programming tools. I have done he
counter
- 详细描述n比特计数器及RTL验证，计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器，可以向上向下计数，并可设置计数值，计数器用异步的方式进行低电平复-A detailed descr iption of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter
Counter-Strike-1.6-patch36_to_protocol48
- Counter-Strike-1.6-patch v 36 to protocol v48
counter
- ASP编写的网页计数器,用于计算访客数量-ASP pages to prepare counter, used to calculate the number of visitors
counter
- 计数器,显示结果在4个数码管上。！~！ 计数器,显示结果在4个数码管上。！~！-COUNTER
counter
- 适用于FPGA Xilinx开发板的Counter程序，计数从0到9999，在板上用4位7段数码管显示，可实现双向计数。-Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
frequency-counter-pic
- C51 designed using the frequency counter, it will automatically switch range, there are testing the data source
counter
- 用verilog写的计数器，可用于分频等多种功能。已经调试成功很好用-Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging
counter
- PIC industrial counter with LCD
counter
- 用VHDL语言编写COUNTER-FPGA VHDL COUNTER
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal
Automatic-Coin-Counter-Matlab-Code
- Automatic Coin Counter Matlab Code
led on off-waiting counter
- led on off with waiting counter
counter
- Counter example for FPGA with VHDL
counter
- counter by implementation vhdl
bcd counter
- Binary counter design in verilog