搜索资源列表
EP3C120
- EP3C120的官方开发板原理图，cyclone iii 系列最大的FPGA.-EP3C120s official development board schematics, cyclone iii series of the largest FPGA.
DDR_allegro
- 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
smo
- 一套DDR OL 游戏源码.也就是所谓的SMO.内置SQL 及其完善的源码 可以用作2次开发等-A set of game-source DDR OL. That is, the so-called SMO. Built-in SQL and its sound source can be used as 2 times the development of
testbench
- ddr sdram controller datd module source code
Flash128MB
- SpearHead的DDRRAM初始化脚本-the DDR initialization scr ipt for spearhead2000
wb-ddr
- 基于Wishbone总线的DDR控制器. -A wraper of DDR controller for wishbone bus.
rtl
- ddr controller in verilog-ddr controller in verilog...............
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
ddr-sdram-verilog-resource
- 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-descr iption the resource code of ddr_sram
ddr
- DDR solution for problem in NPC contest
lpddr_verilog_model
- 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
PRU_memAccessPRUDataRam
- AM335X PRU例子，介绍如何进行PRU与DDR之间的通信-AM335X PRU example, introduce how to communicate beteween PRU and DDR
MYmcb_read_write
- 自己编写的一个赛灵思读写DDR的代码，可以正常读写DDR。-I have written a Xilinx DDR write code that can read and write normal DDR.
mem_interface_top_ddr_controller_0
- 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller
1Gb_DDR3_SDRAM
- DDR2 specification protocol for ddr design
Atmel-SAMA5D3x-DDR-Application-note
- Atmel SAMA5D3X DDR,DDR2,LPDDR2应用说明.-Atmel Microcontroller SAMA5D3x DDR2 LPDDR2 Application note
DDR设计系列
- 很好的PC内存条设计资料，如果你是内存设计的初学者，这里的资料很适合你，值得参考(Very good PC memory design information, if you are a beginner of memory design, the information here is very suitable for you, it is worth reference)
DDR的原理和时序
- 嵌入式DDR时序方面的书籍，对调试时序有帮助(The principle and timing.Rar of DDR)
DDR_Stress_Tester_V1.0.3
- imx6 ddr tool v2, ddr_stress_tester_v1.0.3
9G45DDRtest
- 裸板基于9G45的DDR测试样例，可用户判断DDR的空间大小，读写数据完整性，硬件片选是否正确，多颗DDR芯片硬件组合是否正确，硬件线路是否完整，DDR线路时序是否正常。(DDR bare board test case based on 9G45, the user can determine the DDR size of the space, read and write data integrity, hardware selection is correct, a plurality