搜索资源列表
ddr2_hamdec64
- VHDL实现的64bit海明码解码模块。 可适用于 Xilinx FPGA, Altera FPGA。-VHDL Implement 64bit Hamming Code （decode）
ddr2_hamenc64
- VHDL实现的64bit海明码编码模块。 可适用于 Xilinx FPGA, Altera FPGA。-VHDL Implement 64 bit Hamming Code (encode)
sdram_mt48
- 带DSP/bios的sdram驱动程序，64bit*32M，TI c6416平台，仿照开发板连接-With DSP/bios of sdram driver, 64bit* 32M, TI c6416 platform, modeled on the development of plate connections
shift_reg_ps
- this VHDL program can get a 64bit paralel data and make a serial data with SCLK and WCLK.
scrdsc64
- a simple project with 64 bit scrambler as data encryption/decryption
verilog
- 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operation
test_02
- 在PC端生成离散的正弦波，保存到文件“myfile.txt”中，方便单片机的计算。我是在win7 64bit VC2010中编译通过的。-Generated on the PC side discrete sine wave, to a file " myfile.txt" , the convenient single-chip computing
64bit_doublefloat_adder
- 64位双精度加法器 流水线四拍处理 将53位mantissa 扩展到80位-64bit adder
chufaqi
- 64位除法器，可计算商和余数，时序，测试通过-64bit divider
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
ddr2_sdram_latest.tar
- 1.初始化-Sequenz的RAM 2. Automaic写Sequenz（写入16数据字每一个64位的RAM） 3.自动读Sequenz（从RAM读出的第一个数据字）-1. Init-Sequenz for the RAM 2. Automaic Write-Sequenz (writes 16 Datawords each 64Bit to the RAM) 3. Automatic Read-Sequenz (reads the first Dataword the
vivado_2014-4_2015-2_64bit
- vivado 2014.4-2015.2 64bit的全部license-vivado 2014.4-2015.2 64bit license
64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc
- 64Bit Look Ahead Adder Verilog Code with Testbench
DES
- DES算法实现，64bit，非常好用，有调用说明及代码，通俗易懂-DES algorithm implementation, 64bit, very easy to use, there is a call descr iption and code, easy to understand
Run-Classic-CodeW-on-Win7-64bit
- How to install and run Classic CodeWarrior products on 64-bit Windows 7 PC
ddr3control
- 8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)
Fau
- 使用vhdl写的32位 64位浮点数加法模块、浮点数乘法模块、浮点数除法模块(Use vhdl write 32-bit 64bit floating-point addition module, floating-point multiplication module, floating-point division module)
ti_msp430driver_setup_1.0.1.0
- MSP-FET430UIF Launchpad 开发板 仿真器 WINDOWNS 64BIT 官方认证驱动(MSP-FET430UIF Launchpad development board emulator WINDOWNS 64BIT official authentication driver)