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add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
DSPARMIEEE-754.doc
- 将从CAN总线接收到4字节数据转换成单精度浮点数，每个单精度数据占用4个字节 -Received from the CAN bus, 4 bytes of data into a single precision floating point, single precision data each occupy 4 bytes
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
CPU_voltage_tool
- Intel 479, AMD 939, LGA775, AMD 940, AMD 754, Intel 478, AMD 462, AM2 VID s location
fpu100_latest.tar
- This a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard-This is a 32-bit floating
CORDIC_FPGA
- 摘要：本文在传统CORDIC算法的基础之上，通过增加迭代次数，对参数进行了优化筛选， 提高了运算精度，使设计出的软核能够在精度要求较高的场合中运行，如实时语音、图 像信号处理、滤波技术等。输出数据经过IEEE-754标准化处理，能够直接兼容大多数处 理器，扩展了其应用范围。最终在Altera公司NiosⅡ处理器中通过增加自定义指令的方 式完成了硬件实现。 关键字：CORDIC ,自定义指令, IEEE-754标准化处理。-Abstract: In this paper, ba
emiraga-ieee754-verilog-b7a63aa
- IEEE 754 floating point
GGHGGG
- 三星单片机(276754866)1621显示-Samsung MCU (276,754,866) 1621 shows
Float_point
- 浮点数加/减法器的设计 规格化的浮点数运算器 IEEE标准754 单精度-Floating-point add/subtract device design normalized floating-point arithmetic unit single-precision IEEE Standard 754
sqrt-base-on-fpga
- 对一种改进的不恢复余数的开方算法(non - restoring square - root algorithm)进行了讨论 ,并将其应用于基于 IEEE 754 标准的32 位浮点格式的开方运算中 ,以一款 FPGA 为载体 ,实现了进行运算的基本电路。对目前存在的几种开方 算法进行了评述 ,分析了他们的优缺点 ,提出了改进的不恢复余数开方算法模块化的设计思路与关键电路 ,并分析了仿真和 逻辑综合的结果 ,证明了该算法运算速度较快且占用资源极少的特点。-An improved no
Handbook-of-Floating-Point-Arithmetic---Birkhause
- Floating-point arithmetic (2008), ADD, SUB, MUL, SQRT, FUNCTION (IEEE 754-1985 Standard, IEEE 854-1987 Standard, New IEEE 754-2008 Standard)-Floating-point arithmetic (2008), ADD, SUB, MUL, SQRT, FUNCTION (IEEE 754-1985 Standard, IEEE 854-1987 Stand
floating_point_multiplier_verilog
- This code has written in verilog and it can multiply two floating point number with IEEE 754 standards and the out put of this code is in IEEE 754 standard.We have to put input in binary and the out put is also in binary.
FloatingPoint-Adder
- Implementation of 32-bits Floating Point Adder, based on IEEE 754 Standard
FloatingPointMultiplier
- Implementation of 32-bits Floating Point Multiplier, based on IEEE 754 Standard
FPU
- 32位单精度浮点运算单元,遵从IEEE 754标准，持浮点加、减、乘、除等运算。-32-bit single-precision floating-point unit；comply with the IEEE 754 standard；support floating-point add, subtract, multiply operations.
xunhuanxianshi618754
- 单片机控制循环显示数字618754，程序简单，适合初学者学习。-MCU control loop to display numbers 618,754, the procedure is simple, suitable for beginners to learn.
6.An-FPGA-Based-High-Speed-IEEE-754-Double-Precis
- An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier