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IEEE754Floatingpoint
- IEEE 754 Floating point
VFloat_lib_Nov14_2007
- 遵循 IEEE 754 标准的浮点运算 库 内含 denorm norm fp_add/sub fp_mult fp_devision 可以快速模拟单双精度浮点运算 导师授权使用
add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
IEEE754.zip
- 依據IEEE-754 浮點數標準，將32 bit的Hex,轉換為浮點數,From 32-bit Hexadecimal Representation To Decimal Floating-Point for the IEEE-754 floating-point standard
TMSRV-P-Sources
- 命运2,TM服务器源码，可供开发私服，754版本，NPC*程序-TMSRV+ Sources
DSPARMIEEE-754.doc
- 将从CAN总线接收到4字节数据转换成单精度浮点数，每个单精度数据占用4个字节 -Received from the CAN bus, 4 bytes of data into a single precision floating point, single precision data each occupy 4 bytes
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
4321
- IEEE STD 754 的格式说明和算法的C语言实现IEEE_754-IEEE STD 754 and the algorithm descr iption format C language IEEE_754
TMSrv
- wyd server 754 tmsrv tmsrv_packerprotocol v 754 源代码-wyd server 754 tmsrv tmsrv_packerprotocol v 754 source code
serweb
- 小型的Windows上的web server -A small web server on windows
IEEE754Convertor
- 按照IEEE 754标准对Float和Double类型进行转换-In accordance with the IEEE 754 standard types of Float and Double conversion
IEEE_754_Floating_Point_Conversion_from_floating_
- IEEE-754 Floating-Point Conversion From Decimal Floating-Point To 32-bit and 64-bit Hexadecimal Representations Along with Their Binary Equivalents
GF8051
- Go Fast Floating Point libraries for double float operations bit shifted on an 8bit microcontroller. Includes C and ASM source code, libraries and documentation for Franklin Kiel embedded C compliler.
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
IEEE-754
- IEEE 754 对十六进制数的 解析 可以显示 二进制 以及 正负等-IEEE 754 hexadecimal number parsing
6.An-FPGA-Based-High-Speed-IEEE-754-Double-Precis
- An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
IEEE-754
- 从项目中提取的功能函数，主要是把IEEE 754的浮点数与16进制进行互相转化。文件只提供了函数，需使用者自己重新添加一些头文件进行配置。目前功能的正确性在项目运行过程得到了验证，可以放心使用。代码里有注释。-Float IEEE754 transform to byte