搜索资源列表
basys_3_sch_public
- basys3详细内部结构布局，各个模块都有。-basys3 detailed internal structure and layout, each module has.
basys3_timing
- 基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL-Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL
paomadeng
- 这是一个跑马灯项目，语言为verilog，basys3开发版开发。-this is a project about paomadeng.
vivado_LED_Flow
- 本例程使用vivado2014.4工具，利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。-This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.
SegSimplified
- 本工程使用verilog HDL和vivado2014集成开发环境实现利用xilinx Basys3开发板上4位数码管显示从0到9999的计数器功能。-This project uses verilog HDL to realise counting 0 to 9999 on the 7-seg LED loaded on Xilinx Basys3 board.
ele_lock
- 在Basys3上用两个按钮作为0和1的输入，只有当输入为01011时，LED灯亮。数码管显示输对了几位。-On Basys3 two buttons as inputs 0 and 1, only when the input is 01011 when, LED lights. Digital display to lose a few.
basys3_basic_demo
- basys3_basic_demo，basys3开发平台的例程，在硬件平台已经验证-Basys3_basic_demo basys3 development platform of the routines in hardware platform has been validated
snake
- 自己写的verilog贪吃蛇程序，使用vivado2015.2软件编写综合的，硬件平台是xilinx的basys3平台，当检测到碰撞时，led灯会亮起-Write your own verilog Snake program, using the software to prepare a comprehensive vivado2015.2, the hardware platform is the basys3 xilinx platform, when a collision is det
project_fir_test
- 基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
简易数字钟
- 基于basys3的简易数字钟，可用于vivado开发环境入门，功能有计时和显示模块。(Basys3 based simple digital clock, vivado development environment can be used for entry, function, timing and display module.)
123
- 3路输入，8路输出的译码器，利用FPGA,BASYS3板子实现该功能，文件已有源代码，仿真代码和约束文件。(3 way input, 8 way output decoder, using FPGA, BASYS3 board to achieve the function, the document already has source code, simulation code and constraint files.)
Basys-3-GPIO-2016.4-1
- Test for GPIO for basys3, made by digilent
Basys-3-Keyboard-2016.4-1
- Demo for keyboard, basys3 made by digilent
just_clock
- Just a clock made for basys3 in vivado.
Mux41a
- Basys3 4选一数据选择器代码，初级者学习，在板子上试验过，没问题。(Basys3 4 select a data selector code)
project_PmodMic_PmodAMP2_1
- 用digilent公司的basys3开发板，外接Pmodmic和PmodAMP2模块，实现对声音的采集和复原。程序基于VIVADO 2015.4，附带例化的低通滤波器。实际可用。(Use digisen's basys3 development board, external Pmodmic and PmodAMP2 modules to achieve sound collection and recovery. The program is based on VIVADO 2015.4 wi
project_PmodKYPD
- 用Digilent公司BASYS3开发板和PmodKYPD模块，实现对按键的检测。程序基于VIVADO 2015.4，语言为verilog。(Digilent's BASYS3 development board and PmodKYPD module are used to detect keystrokes. The program is based on VIVADO 2015.4 and the language is verilog.)
FPGA-Projects-master
- FPGA BASYS3 PROJECTS
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
基于basys3的推箱子游戏
- 基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)