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2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
Source_Codes
- 数码显示，键盘，秒表显示：通过TC1 的定时溢出而在LED上动态显示。-digital display, keyboard, stopwatch showed : TC1 regularly overflow and the LED on the dynamic display.
single-key-adjust-clock
- 显示数据在70H-75H单元内，用六位LED共阳数码管显示，P1口输出段码数据，P3口作 扫描控制，每个LED数码管亮1MS时间再逐位循环。 定时器T0、T1溢出周期为50MS，T0为秒计数用， T1为调整时闪烁用， P3.7为调整按钮，P1口 为字符输出口，采用共阳显示管。 -display the data in the 70H-er cell, with a total of six Yang digital LED Display, P1 mouth of
shukongfenpinqi
- 数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the
Digital_filter
- * CONSTRAINTS * This module does not handle data which is considered out of range by the * application(i.e. fixed constants which represent error condition) * * Maximum weight value must be limited to 128 to prevent an overflow * cond
fet440_wdt01
- MSP-FET430P440 Demo - WDT Toggle P5.1 Interval overflow ISR, DCO SMCLK-MSP-FET430P440 Demo - 14d Toggle P5.1 Inte rval overflow ISR, the making of SMCLK
fet440_wdt02
- MSP-FET430P440 Demo - WDT Toggle P5.1 Interval overflow ISR, 32kHz ACLK-MSP-FET430P440 Demo - 14d Toggle P5.1 Inte rval overflow ISR, 32kHz ACLK
mc9s08TIMoverflow
- 利用定时器溢出中断修改时间,并发送新时间-use overflow timer interruption modification time, and this time the new
GP32C-Timer1
- 摩托罗拉单片机的定时器溢出中断的原代码-Motorola MCU overflow timer interruption of the original code
RTOSICCAVR
- UCOS/II for ICCAVR - The version of UCOS/II is 2.04 - the original port was done by Ole Saether for the IAR compiler. Jens E. Holtegaard ported one version using ICCAVR. Joerg Meyer did another port (using Jens port as a start?). This
slac018e
- fet440_wdt_02.s43 - WDT, Toggle P5.1, Interval Overflow ISR, 32kHz ACLK
8051fx_wdog
- This example program shows how to configure PCA Module 4 as a watchdog timer. In this example, the watchdog is configured to overflow after 0xFF00 clock cycles.
fsm
- 检测输入数据中的“10110”序列，并记录检测到的序列的数目，当序列数目大于15时溢出。 输入信号：iclk //输入时钟 rst_ //复位信号 din //输入串行数据 输出信号：[3:0] catch //检测到的序列的数目 overflow //数目大于15 ，溢出
add_overflow
- 一个带overflow功能的加法器的实现，采用Matlab+Simulink
单片机实验三
- P1.7～P1.0接发光二极管L8～L1，要求利用单片机内部定时器1，按方式1工作，每0.01秒T1溢出中断一次。要求编写程序模拟时序控制装置。开机第1秒钟L1、L3亮，第2秒钟L2、L4亮，第3秒钟L5、L7亮，第4秒钟L6、L8亮，第5秒钟L1、L3、L5、L7亮，第6秒钟L2、L4、L6、L8亮，第7秒钟8个发光二极管全亮，……一直循环下去。fosc=11.0592MHz-P1.7 - P1.0 then LED L1 to L8, by using a timer internal mi
pinlvji 频率计VHDL编程
- 频率计VHDL编程。设计一个4位数字显示的十进制频率计，其测量范围为1MHz，测量值通过4个数码管显示以8421BCD码形式输出，可通过开关实现量程控制，量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz)； 当输入信号的频率大于相应量程时，有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measu
pic16c765.rar
- This firmware translates a PS/2 mouse to a USB mouse. The translator firmware is entirely interrupt driven (with the exception of sending the data via USB to the host.) An interrupt is generated when the PS/2 start bit is received, at which tim
main
- 用定时器 1 来改变小灯的状态，T1 每溢出两次，1 个 LED 灯闪烁，1 个 LED 灯改变当前 状态。 -Timer 1 with small lights to change state, T1 overflow twice each, an LED flashes, an LED light to change the current state.
overflow
- 溢出中断代码, C 语言， code warrior 软件-overflow interrupt code, C language, code warrior software
watchdog-overflow-test
- STC89c51单片看门狗溢出测试，也适用于STC其他系列单片机，不过有可能需要稍作修改-STC89c51 single watchdog overflow test, but also for other STC series microcontroller, but there may need to make some modifications