搜索资源列表
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
dengjingdu
- 数字频率计，2015国赛题目，可实现所有功能，整形电路无问题的话，测量结果几乎无误差！-Digital frequency meter, the 2015 National Games, can achieve all the functions, no problem of the plastic circuit, the measurement results are almost no error!
vivado_2014-4_2015-2_64bit
- vivado 2014.4-2015.2 64bit的全部license-vivado 2014.4-2015.2 64bit license
MacPro
- This introduces beginners on a few ways of discovering the basic details about LabVIEW 2015.
led_test
- 实现流水灯的控制verilog程序，源程序vivado 2015.4(Achieve water light control, Verilog procedures)
LAB2
- zynq上实现流水灯的软硬件协同设计，利用vivado 2015.2版本eda软件开发。(Zynq realizes the design of hardware and software of water lamp, and uses vivado version 2015.2 EDA software to develop it.)
XilinxFree.lic
- 这是许可在Xilinx Vivado 2015利用免费的IP核生成(This is the license to utilize free IP core generation in Xilinx Vivado 2015)
2015.06.04+Image_Registration_Batch
- Preprocessing EO-1 Hyperion hyperspectral data to support the application of agricultural indexes
MVA15_Japan_Harris_FPGA_Vivado_source
- Harris 角点检测 FPGA实现 Tak Lon Chao, Kin Hong Wong, "An efficient FPGA implementation of the Harris Corner feature detector" Code:in VHDL and Verliog running on Zedboard(Tak Lon Chao, Kin Hong Wong, "An efficient FPGA implementation
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
vc2015_x64_14.0.24215
- windows 7 安装VIVADO 需要(Microsoft Visual C++ 2015 Redistributable(x64) - 14.0.24215)
project_PmodMic_PmodAMP2_1
- 用digilent公司的basys3开发板，外接Pmodmic和PmodAMP2模块，实现对声音的采集和复原。程序基于VIVADO 2015.4，附带例化的低通滤波器。实际可用。(Use digisen's basys3 development board, external Pmodmic and PmodAMP2 modules to achieve sound collection and recovery. The program is based on VIVADO 2015.4 wi
project_PmodKYPD
- 用Digilent公司BASYS3开发板和PmodKYPD模块，实现对按键的检测。程序基于VIVADO 2015.4，语言为verilog。(Digilent's BASYS3 development board and PmodKYPD module are used to detect keystrokes. The program is based on VIVADO 2015.4 and the language is verilog.)
Vivado_2037
- vivado 2015.4 lisence
rdf0244-zc706-pcie-c-2015-4
- 利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)
Verilog HDL
- 2015年全国电子设计大赛F题，时间间隔测量模块，占空比测量模块，ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)