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AES加密的VHDL源码
- 用VHDL语言实现的AES加密算法的源代码，已经在硬件上下载运行实现了。
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
aes_verilog
- A RTL verilog coding for the project AES, which is a cryptography based concepts
aes
- vhdl implementation of the AES encryption algorithm
aes
- 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
AES!
- AES algorithm very good code tested in xilinx ise tool
AES
- AES implementation in VHDL@!
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
AES
- FPGA Implementation of AES Encryption and Decryption
AES
- 利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性-The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching.
aes-vhdl
- this file contains vhdl code for aes
aes
- AES FPGA verilogHDL实现(AES hardware implementation)
AES 128 ECB Decryption
- Block mode related AES-EBC Encryption
AES 128 ECB Encryption
- Block mode related AES-EBC Decryption
Package for AES-128
- Block mode related AES Package
aes-master
- aes master by vhdl code and decode
aes-project-master
- aes project vhdl FPGA