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DPRAM
- 利用vhdl编写的双端口Ram程序，不带数据纠错处理
WriteDpAddr
- 写DPRAM状态机，Quartus -DPRAM write state machine, Quartus II
ReadDpram
- 读DPRAM状态机，Quartus -DPRAM read state machine, Quartus II
dpram
- FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
fifobaseddprammemory
- This file if about DPram based fifo storage... wirte and read in both ports
DP_RAM.v
- tis about dpram... if u have any quries fell free to ask -tis is about dpram... if u have any quries fell free to ask
dpram_anu
- true dpram with using shared variable
DualPortRam
- VHDL Dpram including clock divider, D4to7, Scan4Digit and of course TOP level as well as testbench info
Desktop.tar
- I ve implemented what oi believe to be a very usefull and easy way to understand the FIFO queue using a DPRAM
dpram
- thi is a dual port ram
dpram
- 包含整个工程，是用verilog来编写，实现双口ram的功能-Contains the entire project is to write Verilog to achieve the function of the dual-port ram
dpramcore
- 基于altera fpga的dpram ipcore 设计，包含整个工程和modelsim仿真文件。读写地址及读写使能是通过数据产生模块来产生。-Altera fpga dpram ipcore design, including engineering and modelsim simulation file. Read and write address and read and write is through the data module.
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
FIFO-queue-using-a-DPRAM
- FIFO queiue using DPRAM goog project
dpram
- vhdl code dual port map
video_center_scan_scaler_alpha_blend
- 本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（frame cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discr iption
dpram
- 在quartus ii平台上，通过代码实现DPRAM，文件夹中包含仿真文件。(generate DPRAM through verilog)
基于AlteraFPGA的DpramIPcore设计
- 基于altera fpga的dpram ipcore 设计，包含整个工程和modelsim仿真文件。读写地址及读写使能是通过数据产生模块来产生。