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Altera Modesim破解版的LICENCE
- Altera Modesim破解版的LICENCE. 下载解压后: 1.直接运行mentorkg.exe(生成的license.txt拷贝到D:\altera\80\modelsim_ae\下或者mentorkg.exe拷贝到此目录下运行). 2.设置环境变量lm_license_file="D:\altera\80\modelsim_ae\license.txt" 3.搞定,Altera Modesim cracked version of the LICENCE.
Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
Am29lv160d
- 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding
micron_sdram_simulation_model
- micron各种规格的SDRAM的仿真模型及详细设计资料，基于verilog语言。-micron variety of SDRAM simulation model and detailed design information, based on the verilog language.
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
Intel8251
- 用VHDL实现Intel 8251的UART功能-Intel 8251 with VHDL realization of the UART Function
exer3
- 3， 采用尽可能少的电路，求出两个在100以内的正整数的最大公约数和最小公倍数。（不许采用mod函数），仿真并综合出电路-3, the circuit using as little as possible, find two positive integers less than the 100 greatest common divisor and least common multiple. (Not allowed to use mod function), and integrated
counter_advanced
- A counter that starts from 0 and increments mod 16 on each rising edge of the clock
i2c_master_model
- i2c仿真model,可用于整体的FPGA仿真系统,用于i2c slave 设计的正确验证-i2c simulation model, the FPGA can be used for the whole simulation system designed for the proper verification i2c slave
5678
- a 256 bit exponential mod verilog code, using fpga to work
mod10asynchro
- this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
mod6asynchro
- this is a code for mod-6 asynchronous counter in verilog.
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal
QAM-Mod
- QAM Modulator verilog code
verilogfile
- 现有16 位寄存器。初始值为0。每个时钟周期寄存器的值会左移1位，并且将输入的数据data_in 作为寄存器的最低位，寄存器原来的最高位将被丢弃。要求每个周期实时输出该16 位寄存器对7 求余的余数data_out[3:0]。-16-bit mod-7 divider.
mod_6counter
- its a mod 6 counter designed using structural modelling
mod_me
- 自己编写的27位宽的，求余模块，成功编译，可以下载到板子上运行-27bit mod block designed by myself ,you can systhesize the file then download the bit file to start board .
mod3
- verilog源代码，实现两种方法的模3运算。-verilog source code，to implement the calculation of mod-3 by two means.
04301090a-u-law
- mod 16 counter using vhdl
PSK-mod-demod-VHDL
- vhdl版本的bpsk调制和解调程序，超级实用-bpsk vhdl mod/demod