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  1. HDLImplementationoftheVariableStepSize

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  2. proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithm
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:218.47kb
    • 提供者:陳柏宇
  1. LinPF

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  2. This a VHDL module that implements linear prediction filter based on NLMS (normalized least mean square). The module takes complex signal as input and output comlex signal (real and imaginary). Tap size is 4, bit precision is set to 12 bits.-This i
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:1.83kb
    • 提供者:徐滨
  1. Float_point

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  2. 浮点数加/减法器的设计 规格化的浮点数运算器 IEEE标准754 单精度-Floating-point add/subtract device design normalized floating-point arithmetic unit single-precision IEEE Standard 754
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:5.46kb
    • 提供者:tong
  1. decimal_divider_nr_norm

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  2. - non-restoring like divider. As in Paper. -- For normalized numbers -- non-restoring like divider. As in Paper. -- For normalized numbers ---------------------------------------------------------------------------------
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.89kb
    • 提供者:Mahmoud
  1. Anderson--Algorithm

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  2. We assume that denominator and numerator are normalized as, for instance, typical for floating-point mantissa values, to the interval 1 ≤ N, D < 2. This normalization step may require essential addition resources (leading-zero detection and two ba
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-30
    • 文件大小:194.12kb
    • 提供者:hooman hematkhah
  1. 5540

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  2. Is a practical method of path planning, Normalized data model, modal vibration, Based on matlab GUI interface design.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-29
    • 文件大小:5kb
    • 提供者:lanjenliekie
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