搜索资源列表
v2.1_ok
- CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用
PCI-T32
- PCI.VHD, THE INTERFACE MODULE WITH PCI AGENT CHIP --v1.0: For CY7C9689, First Version working on L01A chip --V2.0: For simplified PCI Agent, Xilinx and AMD chips
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
OpenCorespcicore
- PCI IP核功能实现，符合V2.2协议-realize pci function
lock_wsh-v2
- FPGA开发，电子密码锁，使用ISE11.1开发而成-The electronic lock
32Kfft
- 32KFFT例程，适用于Quartus II 5.0 or later。- This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later
fft-v2.1.1
- FFT MegaCore Function v2.1.1 VHDL的FFT算法库源代码。-FFT MegaCore Function v2.1.1 VHDL source code for the FFT algorithm library.
PS2USB-v2
- mega手柄 vusb to ps2 -mega handle vusb to ps2
IPTV-V2.2
- IPTV机顶盒技术规范V2.2（修订版）-iptv standard v2.2
controler(v2.0)
- VHDL语言编的一个空调控制系统。cpld实验中的代码-VHDL language a series of air-conditioning control system. the cpld experiments code
I2C
- i2c的通信协议，中英文都有，版本是V2.1-i2c communication protocol, the English have version V2.1
bl-8-gai-add24
- 迸发长度为8的DDR控制器，实现数据的读写，使用赛灵思的V2板子就行验证-Burst length 8 DDR controller, read and write data, and on line verification using Xilinx V2 board
v2
- rs422串口指令控制以及AD7824芯片的数据采集-rs422 serial control timing
V2.tar
- SDIO slave, written in verilog, does not support SPI mode.
UG586-7SeriesDMIUserGuide
- UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )-UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )
Verilog_HDL_v2
- Verilog_HDL_那些事儿_时序篇v2,找了好久才找到的电子书。-Verilog_HDL_ those things _ timing V2, for a long time to find books.
VerilogHDL_module
- VerilogHDL那些事儿_建模篇和Verilog_HDL_那些事儿_时序篇v2是一个系列-VerilogHDL those things _ modeling and Verilog_HDL_ of those things _ timing is a series of V2
pro_1588
- 基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考-Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference
Spartan-6-PCIE_tutorial1
- xilinx Spartan 6 PCIE仿真教程，PIO方式，带有TLP包分析。-XILINX PCIE tutorial device spartan6 PCIE core version V2.4
Spartan-6-PCIE_tutorial2
- xilinx spartan 6 pcie 仿真教程，v2.4版本，主要是讲解如何使用pcie core和自己的用户逻辑级联仿真。-xilinx spartan 6 pcie sim tutorial ，tell readers how to sim using pcie core and user app logic,tool:questasim