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35_486_bus
- 请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第75例是同一个电路的不同部分的描述，可以 一起参考这两个例子的描述。-Please note : The cases include the descr iption of the source file type, version of the study can not be compiled and simulation, if
Nios II处理器中文参考手册
- nios2软件开发手册中文版第8章_MicroC_OSII_tutorial，翻译的不错值得一看-nios2 software development manuals Chinese version of Chapter 8 _MicroC_OSII_tutori al translation of a true eye-catcher
quartus II中文用户教程(英文版的完全翻译）
- quartus II中文用户教程(英文版的完全翻译）,和一切爱好可编程器件的同仁共勉之-Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi
VHDLGoldenReferenceGuide
- 一本非常经典的vhdl设计指导手册（英文版）-a very classic VHDL design instruction manual (English version)
signalgenerater
- 一个简单的多种信号的发生器 包括正玄，锯齿，阶梯等，使用时用quartus 4.0以上版本打开-a simple multiple signal generator including Shogen, sawtooth, the ladder, when used with the above version 4.0 Quartus open
EDA_clock1
- 电子秒表电路，可在开发版上下载运行，verlog开发-electronic stopwatch circuit may download the development version running verlog Development
CapacityRAMModel
- Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
xapp299
- XAPP299 version 1.0 reference design files
8051core_vhdl
- 8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.-8051 kernel (vhdl) This is version 1.1. Of the M C8051 IP core. FPGA operation. have the energy for the study.
uart_core_vhdlORverilog
- 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice versi
mc8051_design
- This is version 1.4 of the MC8051 IP core.
verilog_UART
- This Verilog HDL descr iption implements a UART Version 1.1 : Original Creation 2.1 : added comments
PCI-T32
- PCI.VHD, THE INTERFACE MODULE WITH PCI AGENT CHIP --v1.0: For CY7C9689, First Version working on L01A chip --V2.0: For simplified PCI Agent, Xilinx and AMD chips
UART 源码 (lattice version)
- UART 源码 (lattice version)-UART source (lattice version)
Verilog-golden
- VHDL黄金版，本人费了九牛才找到，帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry
dram
- 4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.
IT51_src.tar
- 這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ-This is the latest version of the amendment after 8051, after debug and achieve a certain company's intention on silicon
quartusii9.1_handbook
- quartusii9.1_handbook用户手册吗，是最新版的altera fpga开发软件资料，altera官方资料，是学习altera fpga的必备资料，（全英文版）中文版我会尽快上传-quartusii9.1_handbook user manual you, is the latest version of the altera fpga software development information, altera official information is essentia
SOPC-development-of-the-Chinese-version-of-Quick-S
- SOPC开发快速入门教程中文版 对SOPC感兴趣的可以参考学习-SOPC development of the Chinese version of the Quick Start Guide can refer interested in learning SOPC
ISE-use-guide-the-full-version
- ISE使用指南完整版。ISE是使用XILINX的FPGA的必备的设计工具.-ISE use guide the full version. XILINX FPGA ISE is to use the necessary design tools.