搜索资源列表
单片机坐标定时器实验
- http://www.edacn.net/cgi-bin/forums.cgi?forum=7&topic=9127下,则R3～R0的输出信号中会有一个为1,但我们还是是无法确定哪一个键被按下,必須要从R3 ～R0 的输出信号与C3～C0的扫描信号共同決定那个按键被按下. 编写VHDL的构思: 外部接口包括: a. INPUT脚 : CLK , R3～R0. b. OUTPUT脚 : C3～C0 , DATA3～DATA0(辨别出的按键值). -7topic http://ww
fifo_01
- 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8 -- 8-bit Identity Comparator -- uses 1993 std VHDL --
decode_for_m68008
- -- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X\"00000\" to X\"01FFF\" -- csbar(1) : X\"40000\" to X\"43FFF\" -- csbar(2) : X\"08000\" to X\"0AFFF\" -- csbar(3) : X\"E000
mo0re_FSM
- -- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding -- dowload from : www.fpga.com.cn
FSM02
- 异步复位状态机 -- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn -asynchronous reset state machine -- State Machine with Asynchronou 's Reset -- dowload from : www.fpga.com.cn
BoothMultiplier
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthe
wave_gen
- 波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH.
EP1C3_12_9_DDS
- 直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参考 http://www.kx-soc.com-direct digital frequency synthesis (DDS) experimental design (Electronic Design Contest tournament title) said other details Please refer to prescribed http://www.kx-soc.com
RS232_Interrupt_Code_niosII
- 串口中断＿niosII.rar 解压密码：www.21control.com
wisbone_2_ahb.tar
- ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Descr iption ---- ---- Implementation of Wishbone_
quartusII8.0_crack.rar
- quartusii8.0正式版破解器,正式版可到官网去下载。http://www.altera.com.cn/,quartusii8.0_crack
grain.rar
- Grain流密码的ＶＨＤＬ源程序，具体说明见 www.ecrypt.eu.org/stream/grainp3.html,The Grain cipher documentation can be obtained at www.ecrypt.eu.org/stream/grainp3.html
VHDL语言实现的arm内核
- 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，
XilinxISE9.2andChinpScopePro9.2Sn
- Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
i2c_Verilog
- Verilog开发的I2c接口模块，如何需要更详细的资料，请参考www.opencores.org网站-Verilog development I2C interface module, how the need for more detailed information, please refer to website www.opencores.org
bingchuan
- 自己编写的并串变换的fpga程序，使用verilog语言-I have written and strings Transform FPGA procedures, the use of Verilog language
cordic_generic
- 本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法，并且在原始的级联型的基础上编写的循环(iterative)型的cordic,可通过generic配置。带一个不可综合和可综合的testbench(for altera)。稍微改动可应用于xilinx fpga-a generic synthesizable cordic with 2 modes: cascade and iterative. based on opencores.org version,
VHDL-Cookbook
- The VHDL book http://www.onlinefreeebooks.net/engineering-ebooks/electrical-engineering/the-vhdl-cookbook-pdf.html
cfq8
- VHDL语言编写8位乘法器非常实用语言绝对正确经过仿真的-VHDL language is very practical 8-bit multiplier is absolutely correct language after simulation
LCD-Driver-And-Keyboard-char-Asm(www.bargh20.com)
- LCD Driver And Keyboard char Asm(www.bargh20.com)