搜索资源列表
divider1
- FPGA 除法器程序-FPGA divider procedures
MATLAB_LUT
- LUT table interpolation without/with divider
VoltageCount
- 计算电路中不同电阻组合时的分压。者作是用于比较器中基准电压采用不同分压方式时的分压电阻值的计算-Calculation circuit for different combinations of the partial pressure resistance. Bidder as is used in the comparator reference voltage divider with a different way that the calculation of the sub-piez
GCDcalulator
- its programs for finding the greatest comman divider
divider
- 流水型除法器，经过FPGA平台验证。宽度可以任意修改，提供计算完毕信号。-Water-type divider, after a FPGA platform validation. Width can be modified to provide the calculation is completed the signal.
fenpin
- 分频器的实现将不同频段的声音信号区分开来，分别给于放大，然后送到相应频段的扬声器中再进行重放-FDCT Frequency Divider
wave
- 这里面是关于微波技术的一些试验程序，和仿真模型，主要有微带线，带状线，功率分配器，支节匹配器-This is on microwave technology, which some experimental procedures, and simulation models, mainly microstrip, stripline, power divider, branch of the matcher
divider
- 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
PFD50
- 分频器，利用D触发器做的2、3、5分频器-Divider, made use of D flip-flop divider 2,3,5
perimeter_md
- Estimation of fractal dimension by divider method
divider
- reed-solomon decoder simulation
TxtDivider
- 超级大文本文件分割器,可以分隔30G以上的文件。-super large text file divider.
cshiyan2012
- 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
divider
- 计算两个整数相除的精确结果，如果存在循环节，则用括号扩起并结束显示-To calculate the two integers accurate results, if there is a circular section, with brackets expand from the end of the show
div16d8
- 16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language
long_division
- divider for long division enhanced algorithm yay awesomeness! This divider works really awesomely correctly we-divider for long division enhanced algorithm yay awesomeness! This divider works really awesomely correctly well
xunfachufaqi
- 从原理到实现的循环除法器的Verilog代码-Circular divider from the principle to the implementation of the Verilog code
divider.c
- 改良型除法器，用来模拟硬件VLSI除法器的工作步骤，是设计硬件的前序步骤-improved divider
1X4_power_splitter2
- 此程序模拟了17X11的正方形光子晶体点阵作为能量偏分器的动态过程。-This program simulates a 17X11 square photonic crystal lattice energy as a partial divider dynamic process.
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.