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divider1
- FPGA 除法器程序-FPGA divider procedures
divider
- 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
divider
- 计算两个整数相除的精确结果，如果存在循环节，则用括号扩起并结束显示-To calculate the two integers accurate results, if there is a circular section, with brackets expand from the end of the show
div16d8
- 16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language
long_division
- divider for long division enhanced algorithm yay awesomeness! This divider works really awesomely correctly we-divider for long division enhanced algorithm yay awesomeness! This divider works really awesomely correctly well
xunfachufaqi
- 从原理到实现的循环除法器的Verilog代码-Circular divider from the principle to the implementation of the Verilog code
divider.c
- 改良型除法器，用来模拟硬件VLSI除法器的工作步骤，是设计硬件的前序步骤-improved divider
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
frequency_divider
- Frequency Divider vhdl source code with test bench
Frequency_divider
- 奇数分频器，通用分频器，占空比1:1分频器， 占空比非1:1分频器-Frequency divider