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DDR+SDRAM控制器verilog代码及中文说明文档
- DDR SDRAM控制器代码，不可多得的源代码。内附详细说明文档。
Adder12_2-6
- This an 12 bits adder in Verilog. it adds two 6 bit nibbles parallel.-This is an 12 bits adder in Verilog. it adds two 6 bit nibbles parallel.
SDRAM_CTRL
- SDRAM 读写的程序 用verilog 写的SDRAM的底层驱动-SDRAM literacy program
cal_pipeline
- 用system verilog 来实习的 1 stage pipeline calculator. It has been successful compiled in Modelsim-System Verilog Calculator