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pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
813S02-Team8
- its bit the system on chip designed in verilog
FPGA_8051core
- FPGA中嵌入8051单片机核的具体操作方法，有图示说明。-8051 single-chip FPGA embedded in the concrete operation of nuclear, there are icons that.
DAC-TLC5620_
- 基于verilog的硬件设计，DAC芯片TLC5620_verilog代码-The DAC chip TLC5620_verilog code verilog-based hardware design
verilog-FAQ
- Low power SRAMs have become a critical component of many VLSI chips. This is true for microprocessors, where on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and main memory. Simu
chuankou7883
- 串口AD的FPGA实现，为verilog程序，芯片为7883，编译已通过-Serial FPGA implementation of AD for verilog program for the 7883 chip, the compiler has passed
ss-single-chip-4k-upscaling
- 4K upscaling ALTERA FPGA verilog
DDR2-controller
- My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another
68013
- 68013USB芯片控制的的verilog代码，经过验证是可用的-Verilog code 68013USB chip control, proven is available
digital-DC_DC-control-chip
- 复旦大学 数字DCDC控制芯片设计 利用matlab中simulink建模 verilog语言实现 对于芯片设计有较*价值-Fudan University digital DCDC control chip design using Simulink matlab modeling Verilog language to achieve a larger reference value for the design of the chip
MPEG_4-codec-chip-development-system
- 浙江大学 基于FPGA的MPEG-4编解码芯片开发系统设计 利用verilog 加以实现，对于在实践中学习verilog很有帮助-Zhejiang University, MPEG-4 codec chip development system based on FPGA use verilog to achieve in practice for learning verilog helpful
18.基于2.4GHz的数字基带系统设计与实现
- 首先设计了 2.4GHz 数字基带系统的架构，该架构包括模拟前端、数字 基带、寄存器、协议处理和 I/O 等模块，其中，数字基带模块由发送子系统和接收 子系统构成。基于该架构，使用 Verilog HDL （hardware descr iption language，硬件 描述语言）设计了数字基带发送子系统，该发送子系统由 PPDU、symbol-to-chip、 chip-to-precode、 CRC 和白化五个模块组成，采用 symbol-to-chip 和 chip-to-pr