• PC100 functionality • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/pr

• Clock frequency: 166, 143 MHz • Fully synchronous all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable

With the burst of a Wanna decryptor [1] in the middle of 2017, secure communication within a network [2] has again triggered the considerable attention. Meanwhile, many feasible methods have been proposed to enhance the data security and it is also