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sfs
- DW 256 DUP(?) STACK1 ENDS DDATA SEGMENT MES1 DB The least number is:$ MES2 DB 0AH,0DH, The largest number is:$ NUMB DB 0D9H,07H,8BH,0C5H,0EBH,04H,9DH,0F9H DDATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DDATA START: MOV AX,DDAT
WIRELESS
- This file contains source code for DS-CDMA transciver using VHDL. it is having two source codes one is for Transmitter and another is for reciever programme.
Spread-Spectrum-Receiver-code
- 基于FPGA的扩频接收机(直扩)vhdl编写的,最好在quartus环境运行。-FPGA-based spread spectrum receiver (DS) vhdl prepared, the best environment to run in quartus.
paper-based-on--radar
- 本文基于某制导雷达信号处理机优化改造工程,介绍了该雷达信号处理机的 接收相干处理(CORP)、动目标显示(MTI)的原理、硬件平台、软件设计、调试以及 优化设计方法。文章首先回顾了该信号处理机相关的信号处理方法,包括数字稳 定校正技术(DS功、参差周期滤波、多次相消器的动目标显示等方法的工作原理和 实现方式,并结合项目进行计算机仿真。其次介绍了信号处理机的组成结构,优 化设计思路,主要功能分配。最后重点讨论了信号处理机的各个模块的工程实现 方法以及数字信号处理
DSSS-Receiver-Sample
- FPGA 上的嵌入式系统设计实例,spartan-3e
ds
- 用VHDL实现的DS18B20温度传感器驱动,有效温度数据位为9位,每92ms刷新一次温度数据。-DS18B20 temperature sensor using VHDL drive, the data bits of the effective temperature of 9 per 92ms refresh time temperature data.
CRC
- 赛灵思的循环冗余校验(CRC),内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the modul