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关于内存的一些概念
- 关于内存的一些概念 原著:阿鸣 1．何为内存模块 (Memory Module)？ 内存模块是指一个印刷电路板表面上有镶嵌数个记忆体芯片chips，而这内存芯片通常是DRAM芯片，但近来系统设计也有使用快取隐藏式芯片镶嵌在内存模块上内存模块是安装在PC 的主机板上的专用插槽(Slot)上镶嵌在Module上DRAM芯片(chips)的数量和个别芯片(chips)的容量，是决定内存模块的设计的主要因素。 - About memory some concepts original: A
shinning
- use dsp5402 dram to let green led flashing in order to test dsp
2410loadGNU
- 2410 nand boot load!（4K DRAM) 0地址开始运行，没有象VIVI拷贝自身到 高端内存运行，可以用它加载UBOOT。 也可以改写它用来引导自己的系统-2410 nand boot load! (4K DRAM) 0 addresses begin, as VIVI not copy itself to high-end memory operation, can be used UBOOT load. It can also rewrite used t
SDRAM_DEVICE_OPERATION
- 三星公司SDRAM（K4S643232H-TC/L60 4 Banks x 512K x 32Bit Synchronous DRAM） 器件操作时序，本中文的页码和原英文对应的页码内容相对应-Samsung SDRAM (K4S643232H-TC/L60 4 x 51 Banks 2K x USB Synchronous DRAM) devices operate timing, the pages of the Chinese and English counterparts of the
C51_DTS
- C51的基于KST-CD111LVD-100 car tuner Driver PLL LC72131 & LA1787 的数字调谐系统-C51-based DRAM-CD111LVD-100 car tuner Driver PLL LC72131
rtl_DRAM
- 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
tlv_bare_ifc
- vhdl SOPC solution sram dram uart -vhdl SOPC solution sram Imperial uart
tlv_ide_ifc
- vhdl SOPC solution sram dram uart -2-vhdl SOPC solution sram Imperial uart -2
tlv_pc_ifc
- vhdl SOPC solution sram dram uart 3-vhdl SOPC solution sram Imperial uart 3
arch_pc_ifc
- vhdl SOPC solution sram dram uart 4-vhdl SOPC solution sram Imperial uart 4
dram
- dram.rar-R3 DARM的基本工作原理，比较详细
dram_control
- 用vhdl描写的通用异步dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL descr iption Universal Asynchronous dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
dram_controller
- 用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL descr iption Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
dram_cntl
- DRAM Controller verilog file
t4
- Explain the very good teaching Ve failed to translate miller overall lack of success of verilog language miller decoding Miller verilog language decoder o 4 Multiplier VHDL language design DRAM Controller verilog file
Verilog-DRAM
- fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
DRAM-manufacture
- 256MDRAM深槽制造工艺，有相关DRAM发展历史等，还有详细的制作工程的图和动画，方便一目了然的了解具体工艺过程-256MDRAM deep grooves manufacturing process, history and other relevant DRAM development, as well as the production of detailed engineering diagrams and animations to facilitate understanding
77433614C51_RAM
- 基于51单片机的DRAM使用，对于理解DRAM很好(The use of DRAM based on the 51 microcontroller is very good for understanding DRAM.)
Allwinner A40i DRAM Support List V1.0
- Allwinner A40i DRAM Support List V1.0