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PIPE_LINING_cpu_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线cpu。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
mcpu_1.06b
- Mcpu is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this cpu is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source
mipsfinal
- 用vhdl设计的一个mips小型cpu，不带流水，有r类，i类，j类指令都有~·-Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*
cpu
- 利用vhdl语言 开发设计一个小型cpu -Development and design using vhdl, a small cpu
test_cpu
- 自己编的小型cpu，可执行简单的代码，作为对开发cpu的尝试。里面包含ROM和cpu。cpu通过状态机执行指令。在Modelsim中仿真通过。-small vhdl cpu,as a example for developing cpu. It is simulated by Modelsim.
intheend
- vhdl设计cpu完整版的vhdl实验程序和下载到实验台上的程序 可能有一些小的错误需要自己调整一下 包括取值、运算、存出、写回和控制几大模块-The full version of the vhdl design cpu vhdl experimental procedures and downloaded to the experimental stage, the program may have some small errors need to adjust the values, c
procesador_1
- vhdl project of a small cpu
cpu_vhdl
- 这是实现一个8位和16位cpu的vhdl代码，虽然支持的指令比较少只有20多条，但对于学习cpu的布线架构很有帮助-This is achieved by an 8-bit and 16-bit cpu vhdl code, although only a relatively small instruction support more than 20, but for learning routing architecture cpu helpful