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pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
JPEG2000
- jpeg 2000 encoder complete document
divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
divide
- It is n-bit sequential divider in verilog language
clk_div
- 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
divide
- 关于verilog的分频程序 等占空比 非等占空比 小数分频 奇数分频-Verilog frequency on the sub-procedures such as the duty cycle of non-duty-cycle fractional odd frequency, etc.
div_n_0_5
- 使用verilog实现任意奇数n+0.5分频，使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
Test
- verilog语言编写的分频程序及其testbench测试文件。fpga开发入门的好例子。-verilog divide written test procedures and testbench files. fpga development of entry-a good example.
8fenpin-verilog
- 用verilog HDL实现8分频，可作为时钟8分频器-Verilog divide by 8 to achieve
divide
- divide模块，实现除法功能。该module是用Verilog编写的，压缩包里包括了设计程序以及测试程序（testbench）。-divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).
verilog--divide-programs
- verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
Verilog-Reference-routines
- verilog 参考例程。适合初学者学习，深入浅出，由简到难，逐步深化，各个击破。 -verilog Reference routines. For beginners learning, easily understood, by Jane to difficult, and gradually deepening, divide and conquer.
VerilogFreq-div
- Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法-Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide
divide
- 用veriog实现的任意位数的除法，在modelism中验证过了已经。-Implementation division with verilog.
verilog--ok
- 二 分 频 二 分 频-Divide divide divide
Verilog-Divide-by-3-Counter
- Verilog Divide by 3 Counter
Verilog-Divide-by-45-Counter
- Verilog Divide by 4.5 Counter
divide-freq
- 基于XILINX芯片的verilog程序。调用DCM模块，完成50MHz转换75MHz，相位偏移90°-XILINX chip based on Verilog program. Call the DCM module to complete the 50MHz conversion, 75MHz, phase shift of 90 degrees
Divide
- This a divider verilog code
divide
- 使用Verilog硬件描述语言编写的分频功能，语言代码简短明了(Frequency division function)