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DDS小数分频
- 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.
mcpu_1.06b
- MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source
my_and
- 此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
VHDL_Beginners
- 国外FPGA的书，很经典，也很基础，可以-It fit to VHDL_Beginners.
counter
- counter in vhdl ... best fit
8051
- 介绍了新的声音采集方法，利用VHDL编写，对声音频谱分析有很强的拟合性-Introduced a new sound collection methods, the use of VHDL writing to sound spectrum analysis has a strong fit of
Touch-Screen_code
- 触摸屏代码，大家可以下载试试，看是否适合你的应用-Touch-screen code, you can download to try to see wheter it fit your application
synplify_pro-text
- 介绍了synplify pro的使用方法，好不容易找到的，欢迎下载，希望与大家共享。-introuducing the text of synplify pro,it is fit for learning the application of the soft
CPLD-FPGA-project-doesnt-fit
- CPLD/FPGA编译时提示“project doesn t fit! do you wish to override some existing settings and/or assignments？解决方法-CPLD/FPGA编译时提示“project doesn t fit! do you wish to override some existing settings and/or assignments？”
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
fit.vhd
- fit implementation in VHDL
uart_rx.fit
- uart core : uart rx fit
synthesize--fit--simulation
- 关于FPGA 设计的流程过程的综合，适配，仿真名词的解释，以及相关注意事项-The attention of the process of FPGA
sdram_controller
- 该模块是一个基于FPGA的SDRAM控制器，该模块有两个接口，一个接口是系统接口，一个连接SDRAM的接口。可以适应不同速度和带宽的SDRAM。-This application note describes the design of a FPGA SDRAM controller.The controller has a system interface on one side and a SDRAM controller for two 16 MB SDRAMs on the other
run time expandable cache
- Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In t
debun1
- 使用D型正反器,使開關防彈跳電路,規劃一個模組電路,也可組合多個模組,來配合多個開關輸入-D-type flip-flop, the switch anti-bounce circuit, planning a modular circuit can also be a combination of multiple modules to fit more than one switch input
4bit-adder
- 4 FIT ADDER FULL EXAMPLE IN VHDL LANGUAGE
ekwgd
- Signal Processing ESPRIT method, Dual-line interpolation FFT harmonic analysis kaiser windows, Least-squares algorithm to fit a three-dimensional plane.
yacew
- Least-squares algorithm to fit a three-dimensional plane, Sampling from a priori probability, calculate the weight, Including single sideband, double sideband, suppressed carrier and quadruple.