搜索资源列表
Vhdl_Golden_Reference_Guide
- vhdl golden reference guide
Behaviouralmodelofasimple8-bitCPU
- 个人认为几个比较实用的VHDL源码之二——Behavioural model of a simple 8-bit CPU-think of a few more practical VHDL source bis -- Behavioral mode l of a simple 8-bit CPU
VHDL_FIR
- 个人认为比较使用的几个VHDL源码之三FIR的源码-personally think that the use of the relatively few VHDL source of the ter FIR FOSS
VHDL_multiplexer
- 个人认为比较使用的几个VHDL源码之四multiplexer的源码-personally think that the use of the relatively few VHDL source 4 multiplexer the source
VHDL_decoder
- 个人认为比较使用的几个VHDL源码之五decoder的源码-personally think that the use of the relatively few 5 VHDL source decoder source code
rs232_send
- rs232 vhdl程序 可以实行异步串行通信,这里只有send-rs232 vhdl procedures implemented asynchronous serial communication, here only send
rs-code
- 基于PLD的RS码编译码器设计，用VHDL语言编写，编译通过，测试结果正确。
mfsk
- vhdl mfsk 多进制数字频率调制(MFSK)也称多元调频或多频制。MFSK系统是 2FSK(二频键控)系统的推广，该系统有 M个 不同的载波频率可供选择．每一个载波频率对应一个 M进制码 元信息，即用多个频率不同的正弦波分别代表不同的数字信号，在某一码元时间内只发送其中一个频率。
Phase_Locked_Loop
- 对一般的PLL及APLL,定点PLL进行了MATLAB SIMULINK仿真，可以由程序直接生成PLL的VHDL和C源代码
automatic-elevator
- 使用VHDL语言编写的基于FPGA的自动升降电梯控制器-VHDL language using FPGA-based controller of automatic elevators
mimo_dectection
- mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过-mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on
suber
- 一位全减器的VHDL语言的实现，用两个半减器实现全减器功能-A full-reducing device implementation of VHDL language, using two and a half to achieve full device functionality by
qpsk_relate
- QPSK解调机设计,采用相关解调,用硬件语言verilog描述-QPSK demodulation machine design, using the relevant demodulation, using the hardware descr iption language verilog
qam_64
- 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
DATA_16QAM_MAP
- 用于WLAN 802.11a的OFDM发射机的数字调制16QAM-For WLAN 802.11a transmitter of the OFDM digital modulation 16QAM
qpsk_relate
- QPSK相关接收机及匹配接收机的verilog实现-QPSK correlation receiver and matching receiver verilog implementation
E1_to_e3_v.2.1
- E1信号到E3复用解复用VHDL代码包括时钟合成-E1 to E3 multiplexing & demultiplexing VHDL code, ，including clock synthesis
led
- 利用VHDL语言完成LED显示基本功能，并且补充了一些特殊功能-LED display using VHDL language to complete basic functions, and added some special features