搜索资源列表
fpga+1602
- 本程序用VHDL语言编程实现FPGA对点阵液晶1602的驱动
clock_VHDL
- VHDL设计的数字时钟，有闹钟、整点报时等功能
8251
- 8251芯片功能的vhdl描述，可以在Quartus下综合
pie_code
- pie edcode编码 程序设计，还有matlab仿真 vhdl硬件实现
clock
- 多功能电子时钟，具有时间显示，时间调整等功能。-Multi-function electronic clocks, time display, time adjustment functions.
sdi_receive
- 本程序是关于SDI 接口的描述，以用FPGA代替相关芯片； sdi_receive-This procedure is described on the SDI interface to use in place of the relevant FPGA chip sdi_receive
sdi_transmit
- 本程序是关于SDI 接口的描述，以用FPGA代替相关芯片； sdi_transmit-This procedure is described on the SDI interface to use in place of the relevant FPGA chip sdi_transmit
reed
- this the completedocumentation and code about reed solomon logic implemented on fpga in verilog.-this is the completedocumentation and code about reed solomon logic implemented on fpga in verilog.
UP3_clock
- 这是一个电子钟程序，采用VHDL开发，在altera的FPGA板上实现。-clock VHDL altera FPGA
cout
- 模可以变计数器。可以实现任意模输入。采用VHDL文本编写。-Mode can be turned counter. Any mode input can be achieved. Text prepared by using VHDL.
qam_map
- Its just a simple 16QAM mapper.
sigmadelta_verilog_code
- sigma delta verilog code and testbench for you to do simulation
garaje
- Is a control of cars in a garage this code is un VHDL-Is a control of cars in a garage this code is un VHDL
AD_SPI
- This VHDL SPI Communication.-This is VHDL SPI Communication.
testfinal---backup1
- Adaptive filter for noise cancellation, vhdl program.
adder_example89
- example of adder using vhdl
vhdl_lab345
- vhdl lab example shifter
VHDL
- 硬件描述语言VHDL语言，用于硬件开发-Hardware descr iption language for hardware development ................... . . .
XHDL4.0.40
- vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-vhdl language and the verilog language conversion tools can easily achieve the conversion of the two languages
VHDL _clav7seg
- clav7seg code source in vhdl