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Verilog-statemachine
- 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
statemachine
- 自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone's attention.
statemachine
- 状态机是FPGA系统工程应用中应用较多的工具 能有效实现系统的逻辑功能
statemachine
- 硬件描述语言的例程，开发板上的例程，大家看看吧。
111
- statemachine it can detecate statemachine
mcu_RTOS_task
- DIY自己的单片机多任务系统。stateMachine+timerTick+q
statemachine
- 用VHDL实现的有限状态机，还有modelsim仿真文件，及仿真结果-VHDL implementation using finite state machine, there modelsim simulation file, and the simulation results
StateMachine
- 状态机的文档、状态机的例子程序和有关状态机的资料，通过文件可以了解labview状态机的原理和编程-The documents state machine, state machine examples of procedures and relevant information on the state machine, through the file labview state machines can understand the principles and programming
statemachine
- 功能描述 ： 用有限状态自动机识别日期,用java 写的-use statemachine to recognise time
keil_DLL_file
- keil C仿真实验板DLL文件：i2c.dll；scope.dll；signalgenerator.dll；statemachine.dll；TimeMeasure.d-keil C simulation board DDL files: i2c.dll scope.dll signalgenerator.dll statemachine.dll TimeMeasure.dll
StateMachine
- 典型的状态机，简单的状态机可以不需要编码，也可以采用one-hot编码方式，如果状态很多时，采用格雷码，能有效避免亚稳态。-A typical state machine, a simple state machine can do without coding, can also be used one-hot encoding, if the state in many cases, the use of Gray code, can effectively avoid metastable
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
StateMachine
- 工作流 状态机 审批工作流 wf+Asp.net approval stateMachine-wf+Asp.net approval stateMachine
StateMachine-based
- FPGA上的利用状态机实现的分频的verilog程序-verilog source code StateMachine-based for FPGA
statemachine
- statemachine状态机可以写状态图的小工具欢迎交流-statemachine,state machine, state diagrams can write a small tool. Welcome exchange
statemachine
- 状态机可以实现几个状态之间的转换,这时使用qt编写的verilog文件-statemachine for inter change between any one of them
LabVIEW201-statemachine
- labview statemachine slides
StateMachine
- 一个有限状态机的编程范例 StateMachine包 状态机管理 IStateMachine.as 状态机接口 MyEvent_Control.as 消息管理,状态管理 MyEvent_Single.as 单个事件 Total.as 实现了状态机接口(IStateMachine)的基类,将其理解为抽象类比较好 A.as 继承基类(Total)的状态机,这个才是真正可用的 B.as 同A Main.as 调用,以及启动 若要使