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DDSFPGA_cylone
- dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
wince+spi
- verilog vcspi file with testbench
calender
- it s content of how to write testbenches using system verilog. it s very important for designer to able to write testbench for given program.
uart
- 基于verilog的串口通信 rs232串口 可以通过八路彩灯判断输入的程序