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2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
binary2bcd
- This build is for developing a \"binary-to-BCD\" converter for use in // displaying numerals in base-10 so that people can read and interpret the // numbers more readily than they could if the numbers were displayed in // binary or hexadecimal
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
TFT.rar
- 基于FPGA的实验。使用FPGA直接控制TFT彩屏，达到显示彩条的效果。使用FPGA连接TFT控制器，使显示一组汉字或一幅图像。 ,FPGA-based experiment. FPGA to directly control the use of TFT color display to show the effect of color. TFT controller using FPGA connected to a group of Chinese characters displaye
Quartus_II_7.0.rar
- Quartus II 7.0工程修复*。修复不能打开的工程。有人在7.2的软件下用本方法也成功修复。 他是修复这个错误： Error: Can t open project -- you do not have permission to write to all the files or create new files in the project s database directory,Quartus II 7.0 Dafa repair works. Restoration pr
mux4
- 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
ethernet.tar
- 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
EP1C3
- fpga LCD 最小系统开发板原理图还内存与SRAM-fpga LCD development board schematics minimum system memory and SRAM is also
s
- 这个是黑金FPGA开发板的部分NIOS源代码集合！有用的随便下！-dahkd dfasfhasfdashfosf df askfksfasf I don t have!
cf_fft_1024_8
- 这是用verilog语言实现的1024点ff程序t-This is achieved using Verilog 1024 language ff procedures point t
wave_produce_VHDL
- --文件名：mine4.vhd。 --功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节
test_uart
- uart VHDL code : include tx,rx,parity bit control
tcounter
- a counter t in vhdl with flip-flop tipe t
fpga_DO
- 根据ModelSim提供的命令或者Tcl/Tk语言的语法，将仿真Cmd流程的仿真命令依次编写到扩展名为“do”的宏文件中，然后直接执行这个DO文件，就可以完成整个仿真流程-According to the order provides ModelSim or Tcl/Tk language syntax, the simulation process simulation Cmd command followed by the preparation of the extension "
t1
- 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M gr
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
IEEE802.3FrameFormat
- IEEE 802.3u (100Base-T)是100兆比特每秒以太网的标准。100Base-T技术中可采用3类传输介质，即100Base-T4、100Base-TX和100Base-FX，它采用4B/5B编码方式-IEEE 802.3u (100Base-T) is 100 megabits per second Ethernet standard. 100Base-T technology in the transmission medium can be used three catego
T
- T触发器 T触发器VHDL实现及报告 FPGA-T flip-flop VHDL implementation and reporting.