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jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
bidirection_reg
- 移位寄存器设计 整个电路由一个主时序进程完成；在每一个时钟的上升沿，根据mode[1:0]的值进行清零、左移或右移操作，在主时序进程中由case语句完成；移位操作由for….loop语句完成8位十六进制数逐位移动。-Shift register design the entire circuit is completed by a master timing process each rising edge of the clock, according to the value of t
FPGA-multiplexer-bus
- FPGA睿智助学板IV代总线与多路复用器Quartus II工程-Generation IV FPGA wise student boards the bus with the Quartus II project multiplexer
demoss
- FPGA的代码verilog语言编写，包括LED与按键验证，数据选择器，编码器，译码器半加器，全加器，适合初学者，已经在板子调试成功，板子是 睿智IV开发板。-FPGA code verilog language, including LED and key authentication, data selection, encoder, decoder and a half adder, full adder, suitable for beginners, it has been succe
demos2
- FPGA的代码verilog语言编写，包括LED流水灯，蜂鸣器，数码管显示。适合初学者，已经在板子调试成功，板子是 睿智IV开发板。-FPGA code verilog language, including LED water lights, buzzers, digital display. Suitable for beginners, it has been successful commissioning of the board, the board is wise IV devel
FPGA
- 睿智开发板配套代码包，板载AD和DA,亲测可用。-Wise development board supporting code package, onboard AD and DA, pro-test available.