完整的DDR控制器设计，包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.

JEDC DDR-5 Standard. DDR-5 标准。(JEDC DDR-5 Standard. JESD79-5 DDR5 Spec Early Draft Rev0.1)