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  1. air_controller

    0下载:
  2. 此为一个空调控制器,是利用FPGA来实现的,他能够完成对室内温度的调节。-this as an air-conditioning controller, is to use the FPGA to realize that he can complete the indoor temperature adjustment.
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:107.24kb
    • 提供者:kyhh
  1. binary2bcd

    0下载:
  2. This build is for developing a \"binary-to-BCD\" converter for use in // displaying numerals in base-10 so that people can read and interpret the // numbers more readily than they could if the numbers were displayed in // binary or hexadecimal
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:41.46kb
    • 提供者:陈朋
  1. Quartus_II_7.0.rar

    0下载:
  2. Quartus II 7.0工程修复*。修复不能打开的工程。有人在7.2的软件下用本方法也成功修复。 他是修复这个错误: Error: Can t open project -- you do not have permission to write to all the files or create new files in the project s database directory,Quartus II 7.0 Dafa repair works. Restoration pr
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-26
    • 文件大小:531.5kb
    • 提供者:gan
  1. DE0_Datasheet

    0下载:
  2. Altera DE0开发板的资料,他的datasheet-Altera DE0 development board information, he datasheet
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-22
    • 文件大小:6.52mb
    • 提供者:Hurley
  1. 8259

    0下载:
  2. 8259中断控制器,参考网上的源码,但自己已经调通,并且应用在控制卡和通信卡上。-8259 interrupt controller, online reference source, but he had transferred Qualcomm, and applications in the control card and communication card.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:179.12kb
    • 提供者:高超
  1. lab1

    0下载:
  2. edk9.1嵌入式开发实验1代码,关于MB何构造一个简单硬件系统-Embedded Development edk9.1 code in Experiment 1, on the MB He constructed a simple hardware system
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:2.37mb
    • 提供者:小贝
  1. DSP_design_based_on_FPGA

    0下载:
  2. 用FPGA设计DSP,2007年上海FPGA高级研修班清华博士贺光辉讲义-FPGA Design with DSP, 2007 in Shanghai FPGA advanced training classes Tsinghua notes Dr. He Guanghui
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.29mb
    • 提供者:david
  1. shukongfenpin

    0下载:
  2. 数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of desig
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-26
    • 文件大小:169.7kb
    • 提供者:邱颖
  1. zhengtaoEDAtest

    0下载:
  2. FPGA入门级学习,自己试验过的VHDL程序,实践学习后进步很快。-Entry-level FPGA learning that he tested the VHDL program, after learning the practice of making rapid progress.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-10
    • 文件大小:2.27mb
    • 提供者:sunzhihui
  1. FPGAebook

    0下载:
  2. FPGA入门级的教程,夏老师的,讲解比较清楚,-FPGA entry-level tutorials, summer teacher to explain more clearly, He He
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-02
    • 文件大小:810.84kb
    • 提供者:wenjiefeng
  1. xuliejianceqi

    0下载:
  2. 序列检测器在数据通信、雷达和遥控领域中用于检测同步识别标志。他是一种用来检测一组或多组序列型号的电路-Sequence detector in data communication, radar and remote areas to detect synchronization marker. He is used to detect one or more types of circuit sequence
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:145.49kb
    • 提供者:冯翔
  1. che

    0下载:
  2. 智能小车寻迹控制程序!!!!何飞飞独家设计!-Smart car tracing control program! ! ! ! He Feifei exclusive design!
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:559byte
    • 提供者:何飞飞
  1. macunit

    0下载:
  2. it is he design of mac unit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:722byte
    • 提供者:gopan
  1. NiosII_Boot

    0下载:
  2. Nios II的Boot过程分析,内容翔实,看了收获很大,详细介绍了几种常见的boot方式 -Nios II of the Boot process analysis, informative, he has learned a great detail some common boot mode
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:99.29kb
    • 提供者:骨头好
  1. FPGA-DEVIDER

    0下载:
  2. 基于FPGA的小数分频器的实现 频率合成技术是现代通讯系统的重要组成部分,他将一个高稳定和高准确度的基准频率,经过四则运算,产生同样稳定度和基准度的频率。-FPGA-based implementation of the fractional divider frequency synthesis technology is an important component of modern communications systems, he has a high stability and
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:65.45kb
    • 提供者:lishaohui
  1. jicun

    0下载:
  2. 32位32个寄存器组程序设计,用vhdl语言-module registers071221049 ( input [4:0]s1,s2, input [4:0] wd, input [31:0] data, input wre, clk, input he,hc,le,lc, output [31:0] out1, output [31:0] out2 )
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:610byte
    • 提供者:jari
  1. etyft

    0下载:
  2. 123 紧固件钢结构竟复活方法还库呼呼有客户部衣服和发叫一分耕耘给软硬件-sorry i you she he it vidieo
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-14
    • 文件大小:4.09kb
    • 提供者:caijiabao
  1. VHDL-Beginners-Book

    0下载:
  2. This report was written for both the professional engineer who has never designed using programmable logic devices and for the new engineer embarking on their exciting career in electronics design. To accommodate this the following navigation s
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-21
    • 文件大小:5.95mb
    • 提供者:mutu
  1. alu

    0下载:
  2. In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors conta
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:2.36kb
    • 提供者:Andrew
  1. biaojueqi

    0下载:
  2. 一个四人表决器,区分了主裁判和副裁判的身份,主裁判比较牛X,他同意了就通过-A four-person voting, the main distinction between the identity of the referee and deputy referees, the referee more cattle X, he agreed on the adoption of
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:114.49kb
    • 提供者:张辛楠
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